X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/f26748f71f3f39de15a1c07f95c15f8c4481f452..06ad3a30038ac8ca45dd7b0c34213c0c8335c17c:/GBZ80Core.v?ds=inline

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 3cd46e3..96e4dcd 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -45,6 +45,7 @@
 `define INSN_JP_HL			8'b11101001
 `define INSN_JR_imm			8'b00011000
 `define INSN_JRCC_imm		8'b001xx000
+`define INSN_INCDEC16		8'b00xxx011
 
 `define INSN_cc_NZ			2'b00
 `define INSN_cc_Z				2'b01
@@ -408,8 +409,8 @@ module GBZ80Core(
 						address <= {registers[`REG_SPH],registers[`REG_SPL]};
 					end
 				1:	begin	// SPECIAL CASE: cycle does NOT increase linearly with ret!
-						`EXEC_INC_PC;
-						case (opcode[4:3])	// cycle 1 is skipped if we are not retcc
+						`EXEC_INC_PC;	// cycle 1 is skipped if we are not retcc
+						case (opcode[4:3])
 						`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
 						`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
 						`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
@@ -523,6 +524,34 @@ module GBZ80Core(
 					end
 				endcase
 			end
+			`INSN_INCDEC16: begin
+				case (cycle)
+				0: begin
+						case (opcode[5:4])
+						`INSN_reg16_BC:	begin
+							tmp <= registers[`REG_B];
+							tmp2 <= registers[`REG_C];
+						end
+						`INSN_reg16_DE:	begin
+							tmp <= registers[`REG_D];
+							tmp2 <= registers[`REG_E];
+						end
+						`INSN_reg16_HL:	begin
+							tmp <= registers[`REG_H];
+							tmp2 <= registers[`REG_L];
+						end
+						`INSN_reg16_SP:	begin
+							tmp <= registers[`REG_SPH];
+							tmp2 <= registers[`REG_SPL];
+						end
+						endcase
+					end
+				1: begin
+						`EXEC_INC_PC;
+						`EXEC_NEWCYCLE;
+					end
+				endcase
+			end
 			default:
 				$stop;
 			endcase
@@ -800,7 +829,7 @@ module GBZ80Core(
 				4:	begin
 						{registers[`REG_SPH],registers[`REG_SPL]} <=
 							{registers[`REG_SPH],registers[`REG_SPL]} + 2;
-						if (opcode[4] && (opcode != `INSN_RETCC))	/* RETI */
+						if (opcode[4] && opcode[0])	/* RETI */
 							ie <= 1;
 					end
 				endcase
@@ -841,6 +870,32 @@ module GBZ80Core(
 						{tmp[7]?8'hFF:8'h00,tmp};
 				endcase
 			end
+			`INSN_INCDEC16: begin
+				case (cycle)
+				0:	{tmp,tmp2} <= {tmp,tmp2} +
+						(opcode[3] ? 16'hFFFF : 16'h0001);
+				1: begin
+						case (opcode[5:4])
+						`INSN_reg16_BC:	begin
+							registers[`REG_B] <= tmp;
+							registers[`REG_C] <= tmp2;
+						end
+						`INSN_reg16_DE:	begin
+							registers[`REG_D] <= tmp;
+							registers[`REG_E] <= tmp2;
+						end
+						`INSN_reg16_HL:	begin
+							registers[`REG_H] <= tmp;
+							registers[`REG_L] <= tmp2;
+						end
+						`INSN_reg16_SP:	begin
+							registers[`REG_SPH] <= tmp;
+							registers[`REG_SPL] <= tmp2;
+						end
+						endcase
+					end
+				endcase
+			end
 			default:
 				$stop;
 			endcase