X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/ef6fbe3130c958177759bd99cf24a6c3edc4693c..a02672555adf08bfd6755cf70599895dd2155a24:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index cb231c2..afa4495 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -395,16 +395,18 @@ module GBZ80Core(
 						rd <= 1;
 					end
 				2:	begin
+						`EXEC_INC_PC;
+					end
+				3:	begin
 						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
 						wdata <= registers[`REG_PCH];
 						wr <= 1;
 					end
-				3:	begin
+				4:	begin
 						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
 						wdata <= registers[`REG_PCL];
 						wr <= 1;
 					end
-				4:	begin /* nothing happens on the bus next cycle! */ end
 				5:	begin
 						`EXEC_NEWCYCLE;	/* do NOT increment the PC */
 					end
@@ -680,15 +682,15 @@ module GBZ80Core(
 					end
 				3: begin
 						cycle <= 4;
-						registers[`REG_PCH] <= tmp2;
 					end
 				4: begin
 						cycle <= 5;
-						registers[`REG_PCL] <= tmp;
+						registers[`REG_PCH] <= tmp2;
 					end
 				5: begin
 						{registers[`REG_SPH],registers[`REG_SPL]} <=
 							{registers[`REG_SPH],registers[`REG_SPL]} - 2;
+						registers[`REG_PCL] <= tmp;
 						cycle <= 0;
 					end
 				endcase
@@ -705,26 +707,22 @@ endmodule
 module ROM(
 	input [15:0] address,
 	inout [7:0] data,
+	input clk,
 	input wr, rd);
 
 	reg [7:0] rom [2047:0];
 	initial $readmemh("rom.hex", rom);
 
 	wire decode = address[15:13] == 0;
-	reg [7:0] odata;
-	wire idata = data;
+	wire [7:0] odata = rom[address[11:0]];
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-	
-	always @(wr or rd)
-	begin
-		if (decode && rd)
-			odata <= rom[address];
-	end
+	//assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
 
 module InternalRAM(
 	input [15:0] address,
 	inout [7:0] data,
+	input clk,
 	input wr, rd);
 	
 	reg [7:0] ram [8191:0];
@@ -734,22 +732,53 @@ module InternalRAM(
 	wire idata = data;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(rd or wr)
+	always @(negedge clk)
 	begin
 		if (decode && rd)
-			odata <= ram[address];
+			odata <= ram[address[12:0]];
 		else if (decode && wr)
-			ram[address] <= idata;
+			ram[address[12:0]] <= data;
 	end
 endmodule
 
-module TestBench();
-	reg clk = 0;
+//module Switches(
+//	input [15:0] address,
+//	inout [7:0] data,
+//	input clk,
+//	input wr, rd,
+//	input [7:0] switches,
+//	output reg [7:0] ledout);
+	
+//	wire decode = address == 16'hFF51;
+//	reg [7:0] odata;
+//	wire idata = data;
+//	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	
+//	always @(negedge clk)
+//	begin
+//		if (decode && rd)
+//			odata <= switches;
+//		else if (decode && wr)
+//			ledout <= data;
+//	end
+//endmodule
+
+module CoreTop(
+	input iclk,
+	output wire [7:0] leds,
+	output serio);
+	
+	wire clk;
+	IBUFG ibuf (.O(clk), .I(iclk));
+
 	wire [15:0] addr;
 	wire [7:0] data;
 	wire wr, rd;
 	
-	always #10 clk <= ~clk;
+	wire [7:0] swleds;
+	
+	assign leds = clk?{rd,wr,addr[5:0]}:data[7:0];
+
 	GBZ80Core core(
 		.clk(clk),
 		.busaddress(addr),
@@ -760,12 +789,59 @@ module TestBench();
 	ROM rom(
 		.address(addr),
 		.data(data),
+		.clk(clk),
 		.wr(wr),
 		.rd(rd));
 	
-	InternalRAM ram(
-		.address(addr),
-		.data(data),
-		.wr(wr),
-		.rd(rd));
+	assign serio = 0;
 endmodule
+
+//module TestBench();
+//	reg clk = 0;
+//	wire [15:0] addr;
+//	wire [7:0] data;
+//	wire wr, rd;
+	
+//	wire [7:0] leds;
+//	wire [7:0] switches;
+	
+//	always #10 clk <= ~clk;
+//	GBZ80Core core(
+//		.clk(clk),
+//		.busaddress(addr),
+//		.busdata(data),
+//		.buswr(wr),
+//		.busrd(rd));
+	
+//	ROM rom(
+//		.clk(clk),
+//		.address(addr),
+//		.data(data),
+//		.wr(wr),
+//		.rd(rd));
+	
+//	InternalRAM ram(
+//		.address(addr),
+//		.data(data),
+//		.clk(clk),
+//		.wr(wr),
+//		.rd(rd));
+
+//	wire serio;
+//	UART uart(
+//		.addr(addr),
+//		.data(data),
+//		.clk(clk),
+//		.wr(wr),
+//		.rd(rd),
+//		.serial(serio));
+	
+//	Switches sw(
+//		.clk(clk),
+//		.address(addr),
+//		.data(data),
+//		.wr(wr),
+//		.rd(rd),
+//		.switches(switches),
+//		.leds(leds));
+//endmodule