X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/ee31adcb22c5011aeaaa0149ee22fa18e45317a5..6bd4619bee74d76a525f7def9ac56ffcf114a3f4:/System.v

diff --git a/System.v b/System.v
index dbcfaa4..0e464f5 100644
--- a/System.v
+++ b/System.v
@@ -15,6 +15,28 @@ module ROM(
 	//assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
 
+module MiniRAM(			/* XXX will need to go INSIDE the CPU for when we do DMA */
+	input [15:0] address,
+	inout [7:0] data,
+	input clk,
+	input wr, rd);
+	
+	reg [7:0] ram [127:0];
+	
+	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
+	reg [7:0] odata;
+	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	
+	always @(negedge clk)
+	begin
+		if (decode)	// This has to go this way. The only way XST knows how to do
+		begin				// block ram is chip select, write enable, and always
+			if (wr)		// reading. "else if rd" does not cut it ...
+				ram[address[6:0]] <= data;
+			odata <= ram[address[6:0]];
+		end
+	end
+
 module InternalRAM(
 	input [15:0] address,
 	inout [7:0] data,
@@ -173,6 +195,14 @@ module CoreTop(
 		.wr(wr),
 		.rd(rd)
 		);
+	
+	MiniRAM mram(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd)
+		);
 
 	Timer tmr(
 		.clk(clk),