X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/ec7274034775dc5e053ff3c96bd141ac50b4fc81..74610a872e3bead82589e6ea786e928f319540e4:/LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 5089129..a198c45 100644
--- a/LCDC.v
+++ b/LCDC.v
@@ -27,11 +27,10 @@ module LCDC(
 	/***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
 	reg clk4 = 0;
 	always @(posedge clk)
-		clk4 = ~clk4;
-	assign lcdclk = clk4;
+		clk4 <= ~clk4;
 	
 	/***** LCD control registers *****/
-	reg [7:0] rLCDC = 8'h91;
+	reg [7:0] rLCDC = 8'h00;
 	reg [7:0] rSTAT = 8'h00;
 	reg [7:0] rSCY = 8'b00;
 	reg [7:0] rSCX = 8'b00;
@@ -63,8 +62,8 @@ module LCDC(
 	reg [8:0] posx = 9'h000;
 	reg [7:0] posy = 8'h00;
 	
-	wire vraminuse = (posx < 163) && (posy < 144);
-	wire oaminuse = (posx > 369) && (posy < 144);
+	wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];
+	wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];
 	
 	wire display = (posx > 2) && (posx < 163) && (posy < 144);
 	
@@ -77,8 +76,9 @@ module LCDC(
 	wire [7:0] vxpos = rSCX + posx - 3;
 	wire [7:0] vypos = rSCY + posy;
 	
-	assign lcdvs = (posy == 153) && (posx == 2);
-	assign lcdhs = (posx == 2);
+	assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
+	assign lcdhs = (posx == 2) && rLCDC[7];
+	assign lcdclk = clk4;
 	
 	wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
 	wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
@@ -145,7 +145,8 @@ module LCDC(
 	reg [7:0] tileno;
 	wire [10:0] tileaddr = {tileno, vypos[2:0]};
 	reg [7:0] tilehigh, tilelow;
-	assign pixdata = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+	wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+	assign pixdata = {rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
 	
 	wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
 	wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
@@ -153,14 +154,13 @@ module LCDC(
 	wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
 	wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
 	
-	always @(negedge clk)
+	always @(posedge clk)
+	begin
 		if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
 			tileno <= bgmap1[bgmapaddr_in];
 			if (wr && decode_bgmap1 && ~vraminuse)
 				bgmap1[bgmapaddr_in] <= data;
 		end
-	
-	always @(negedge clk)
 		if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
 			tilehigh <= tiledatahigh[tileaddr_in];
 			tilelow <= tiledatalow[tileaddr_in];
@@ -169,6 +169,7 @@ module LCDC(
 			if (wr && ~addr[0] && decode_tiledata && ~vraminuse)
 				tiledatalow[tileaddr_in] <= data;
 		end
+	end
   
 	/***** Bus interface *****/
 	assign data = rd ?
@@ -189,7 +190,7 @@ module LCDC(
 			 8'bzzzzzzzz) :
 		8'bzzzzzzzz;
   
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (wr)
 			case (addr)