X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/eb0f2fe1637a4c6b4532ae08ff7b0af3bf39aef0..3ad960bdb71efcbb1dfd436163085da0d70eb699:/insn_alu8.v

diff --git a/insn_alu8.v b/insn_alu8.v
new file mode 100644
index 0000000..8470e27
--- /dev/null
+++ b/insn_alu8.v
@@ -0,0 +1,115 @@
+`ifdef EXECUTE
+	`INSN_ALU8: begin
+		if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+			// fffffffff fuck your shit, read from (HL) :(
+			rd <= 1;
+			address <= {registers[`REG_H], registers[`REG_L]};
+		end else begin
+			`EXEC_NEWCYCLE;
+			`EXEC_INC_PC;
+			case (opcode[2:0])
+			`INSN_reg_A:	tmp <= registers[`REG_A];
+			`INSN_reg_B:	tmp <= registers[`REG_B];
+			`INSN_reg_C:	tmp <= registers[`REG_C];
+			`INSN_reg_D:	tmp <= registers[`REG_D];
+			`INSN_reg_E:	tmp <= registers[`REG_E];
+			`INSN_reg_H:	tmp <= registers[`REG_H];
+			`INSN_reg_L:	tmp <= registers[`REG_L];
+			`INSN_reg_dHL:	tmp <= rdata;
+			endcase
+		end
+	end
+`endif
+
+`ifdef WRITEBACK
+	`INSN_ALU8: begin
+		if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+			/* Sit on our asses. */
+		end else begin		/* Actually do the computation! */
+			case (opcode[5:3])
+			`INSN_alu_ADD: begin
+				registers[`REG_A] <=
+					registers[`REG_A] + tmp;
+				registers[`REG_F] <=
+					{ /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
+					  /* N */ 1'b0,
+					  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+					  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+					  registers[`REG_F][3:0]
+					};
+			end
+			`INSN_alu_ADC: begin
+				registers[`REG_A] <=
+					registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
+				registers[`REG_F] <=
+					{ /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
+					  /* N */ 1'b0,
+					  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
+					  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
+					  registers[`REG_F][3:0]
+					};
+			end
+			`INSN_alu_SUB: begin
+				registers[`REG_A] <=
+					registers[`REG_A] - tmp;
+				registers[`REG_F] <=
+					{ /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+					  /* N */ 1'b1,
+					  /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+					  /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+					  registers[`REG_F][3:0]
+					};
+			end
+			`INSN_alu_SBC: begin
+				registers[`REG_A] <=
+					registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
+				registers[`REG_F] <=
+					{ /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+					  /* N */ 1'b1,
+					  /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
+					  /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
+					  registers[`REG_F][3:0]
+					};
+			end
+			`INSN_alu_AND: begin
+				registers[`REG_A] <=
+					registers[`REG_A] & tmp;
+				registers[`REG_F] <=
+					{ /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
+					  3'b010,
+					  registers[`REG_F][3:0]
+					};
+			end
+			`INSN_alu_OR: begin
+				registers[`REG_A] <=
+					registers[`REG_A] | tmp;
+				registers[`REG_F] <=
+					{ /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
+					  3'b000,
+					  registers[`REG_F][3:0]
+					};
+			end
+			`INSN_alu_XOR: begin
+				registers[`REG_A] <=
+					registers[`REG_A] ^ tmp;
+				registers[`REG_F] <=
+					{ /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
+					  3'b000,
+					  registers[`REG_F][3:0]
+					};
+			end
+			`INSN_alu_CP: begin
+				registers[`REG_F] <=
+					{ /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+					  /* N */ 1'b1,
+					  /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+					  /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+					  registers[`REG_F][3:0]
+					};
+			end
+			default:
+				$stop;
+			endcase
+		end
+	end
+`endif