X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/e7fb589a21ee26ad897e03cbd0d7a647d9cd97e5..e29171aa4e057f7c1a2682a0dfd1836beeb71651:/GBZ80Core.v?ds=inline diff --git a/GBZ80Core.v b/GBZ80Core.v index 1182b32..8970e5d 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -146,9 +146,12 @@ module GBZ80Core( input clk, - output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */ - inout [7:0] busdata, - output reg buswr, output reg busrd, + inout [15:0] bus0address, /* BUS_* is latched on STATE_FETCH. */ + inout [7:0] bus0data, + inout bus0wr, bus0rd, + inout [15:0] bus1address, /* BUS_* is latched on STATE_FETCH. */ + inout [7:0] bus1data, + inout bus1wr, bus1rd, input irq, input [7:0] jaddr, output reg [1:0] state); @@ -167,7 +170,28 @@ module GBZ80Core( reg [7:0] tmp, tmp2; /* Generic temporary regs. */ reg [7:0] buswdata; - assign busdata = buswr ? buswdata : 8'bzzzzzzzz; + wire [7:0] busdata; + + reg [15:0] busaddress; + reg buswr, busrd; + + reg bootstrap_enb; + + wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF)) /* 0 or 1 depending on which bus */ + `ifdef isim + || (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */ + `endif + ; + + assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz; + assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz; + assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz; + assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz; + assign busdata = (bus == 0) ? bus0data : bus1data; + assign bus0rd = (bus == 0) ? busrd : 1'b0; + assign bus1rd = (bus == 1) ? busrd : 1'b0; + assign bus0wr = (bus == 0) ? buswr : 1'b0; + assign bus1wr = (bus == 1) ? buswr : 1'b0; reg ie, iedelay; @@ -257,9 +281,10 @@ module GBZ80Core( state <= `STATE_WRITEBACK; cycle <= 0; twobyte <= 0; + bootstrap_enb <= 1; end - always @(posedge clk) + always @(negedge clk) /* Set things up at the negedge to prepare for the posedge. */ case (state) `STATE_FETCH: begin if (newcycle) begin @@ -273,6 +298,17 @@ module GBZ80Core( if (wr) buswdata <= wdata; end + end + `STATE_DECODE: begin /* Make sure this only happens for one clock. */ + buswr <= 0; + busrd <= 0; + end + endcase + + always @(posedge clk) + case (state) + `STATE_FETCH: begin + /* Things are set up in negedge so that something looking on posedge will get his shit. */ state <= `STATE_DECODE; end `STATE_DECODE: begin @@ -284,26 +320,28 @@ module GBZ80Core( opcode <= `INSN_VOP_INTR; else opcode <= {1'b0,busdata}; - rdata <= busdata; newcycle <= 0; + rdata <= busdata; cycle <= 0; end else begin - if (rd) rdata <= busdata; + if (rd) rdata <= busdata; /* Still valid because peripherals are now expected to keep it held valid. */ cycle <= cycle + 1; end if (iedelay) begin ie <= 1; iedelay <= 0; end - buswr <= 0; - busrd <= 0; wr <= 0; rd <= 0; + buswr <= 0; + busrd <= 0; address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened. wdata <= 8'bxxxxxxxx; state <= `STATE_EXECUTE; end `STATE_EXECUTE: begin + if (opcode[7:0] === 8'bxxxxxxxx) + $stop; casex (opcode) `define EXECUTE `include "allinsns.v"