X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/e7fb589a21ee26ad897e03cbd0d7a647d9cd97e5..91c74a3f7409b5ac9bdbd46fbff13c513b19bc9c:/GBZ80Core.v diff --git a/GBZ80Core.v b/GBZ80Core.v index 1182b32..ec882da 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -146,9 +146,12 @@ module GBZ80Core( input clk, - output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */ - inout [7:0] busdata, - output reg buswr, output reg busrd, + inout [15:0] bus0address, /* BUS_* is latched on STATE_FETCH. */ + inout [7:0] bus0data, + inout bus0wr, bus0rd, + inout [15:0] bus1address, /* BUS_* is latched on STATE_FETCH. */ + inout [7:0] bus1data, + inout bus1wr, bus1rd, input irq, input [7:0] jaddr, output reg [1:0] state); @@ -167,7 +170,24 @@ module GBZ80Core( reg [7:0] tmp, tmp2; /* Generic temporary regs. */ reg [7:0] buswdata; - assign busdata = buswr ? buswdata : 8'bzzzzzzzz; + wire [7:0] busdata; + + reg [15:0] busaddress; + reg buswr, busrd; + + reg bootstrap_enb; + + wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF)); /* 0 or 1 depending on which bus */ + + assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz; + assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz; + assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz; + assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz; + assign busdata = (bus == 0) ? bus0data : bus1data; + assign bus0rd = (bus == 0) ? busrd : 1'bz; + assign bus1rd = (bus == 1) ? busrd : 1'bz; + assign bus0wr = (bus == 0) ? buswr : 1'bz; + assign bus1wr = (bus == 1) ? buswr : 1'bz; reg ie, iedelay; @@ -257,6 +277,7 @@ module GBZ80Core( state <= `STATE_WRITEBACK; cycle <= 0; twobyte <= 0; + bootstrap_enb <= 1; end always @(posedge clk)