X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/e7fb589a21ee26ad897e03cbd0d7a647d9cd97e5..2854e3991ab66f6fb954aba96caf7875d049431e:/System.v?ds=sidebyside

diff --git a/System.v b/System.v
index cdcee09..1872e51 100644
--- a/System.v
+++ b/System.v
@@ -6,16 +6,33 @@ module ROM(
 	input clk,
 	input wr, rd);
 
+	reg [7:0] odata;
+
+	// synthesis attribute ram_style of rom is block
 	reg [7:0] rom [1023:0];
 	initial $readmemh("rom.hex", rom);
 
 	wire decode = address[15:13] == 0;
-	wire [7:0] odata = rom[address[10:0]];
+	always @(posedge clk)
+		odata <= rom[address[10:0]];
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-	//assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
 
-module MiniRAM(			/* XXX will need to go INSIDE the CPU for when we do DMA */
+module BootstrapROM(
+	input [15:0] address,
+	inout [7:0] data,
+	input clk,
+	input wr, rd);
+
+	reg [7:0] brom [255:0];
+	initial $readmemh("bootstrap.hex", brom);
+
+	wire decode = address[15:8] == 0;
+	wire [7:0] odata = brom[address[7:0]];
+	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+endmodule
+
+module MiniRAM(
 	input [15:0] address,
 	inout [7:0] data,
 	input clk,
@@ -27,7 +44,7 @@ module MiniRAM(			/* XXX will need to go INSIDE the CPU for when we do DMA */
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode)	// This has to go this way. The only way XST knows how to do
 		begin				// block ram is chip select, write enable, and always
@@ -51,7 +68,7 @@ module InternalRAM(
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode)	// This has to go this way. The only way XST knows how to do
 		begin				// block ram is chip select, write enable, and always
@@ -74,7 +91,7 @@ module Switches(
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode && rd)
 			odata <= switches;
@@ -125,9 +142,9 @@ module CoreTop(
 	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 `endif
 
-	wire [15:0] addr;	
-	wire [7:0] data;
-	wire wr, rd;
+	wire [15:0] addr [1:0];
+	wire [7:0] data [1:0];
+	wire wr [1:0], rd [1:0];
 	
 	wire irq, tmrirq, lcdcirq, vblankirq;
 	wire [7:0] jaddr;
@@ -135,31 +152,42 @@ module CoreTop(
 	
 	GBZ80Core core(
 		.clk(clk),
-		.busaddress(addr),
-		.busdata(data),
-		.buswr(wr),
-		.busrd(rd),
+		.bus0address(addr[0]),
+		.bus0data(data[0]),
+		.bus0wr(wr[0]),
+		.bus0rd(rd[0]),
+		.bus1address(addr[1]),
+		.bus1data(data[1]),
+		.bus1wr(wr[1]),
+		.bus1rd(rd[1]),
 		.irq(irq),
 		.jaddr(jaddr),
 		.state(state));
 	
+	BootstrapROM brom(
+		.address(addr[1]),
+		.data(data[1]),
+		.clk(clk),
+		.wr(wr[1]),
+		.rd(rd[1]));
+	
 	ROM rom(
-		.address(addr),
-		.data(data),
+		.address(addr[0]),
+		.data(data[0]),
 		.clk(clk),
-		.wr(wr),
-		.rd(rd));
+		.wr(wr[0]),
+		.rd(rd[0]));
 	
 	wire lcdhs, lcdvs, lcdclk;
 	wire [2:0] lcdr, lcdg;
 	wire [1:0] lcdb;
 	
 	LCDC lcdc(
-		.addr(addr),
-		.data(data),
 		.clk(clk),
-		.wr(wr),
-		.rd(rd),
+		.addr(addr[0]),
+		.data(data[0]),
+		.wr(wr[0]),
+		.rd(rd[0]),
 		.lcdcirq(lcdcirq),
 		.vblankirq(vblankirq),
 		.lcdclk(lcdclk),
@@ -184,8 +212,8 @@ module CoreTop(
 		.vgab(b));
 	
 	AddrMon amon(
-		.addr(addr), 
 		.clk(clk), 
+		.addr(addr[0]),
 		.digit(digits), 
 		.out(seven),
 		.freeze(buttons[0]),
@@ -196,55 +224,55 @@ module CoreTop(
 			                   4'b0100) );
 	 
 	Switches sw(
-		.address(addr),
-		.data(data),
 		.clk(clk),
-		.wr(wr),
-		.rd(rd),
+		.address(addr[0]),
+		.data(data[0]),
+		.wr(wr[0]),
+		.rd(rd[0]),
 		.ledout(leds),
 		.switches(switches)
 		);
 
 	UART nouart (	/* no u */
-		.clk(clk), 
-		.wr(wr), 
-		.rd(rd), 
-		.addr(addr), 
-		.data(data), 
+		.clk(clk),
+		.addr(addr[0]),
+		.data(data[0]),
+		.wr(wr[0]),
+		.rd(rd[0]),
 		.serial(serio)
 		);
 
 	InternalRAM ram(
-		.address(addr),
-		.data(data),
 		.clk(clk),
-		.wr(wr),
-		.rd(rd)
+		.address(addr[0]),
+		.data(data[0]),
+		.wr(wr[0]),
+		.rd(rd[0])
 		);
 	
 	MiniRAM mram(
-		.address(addr),
-		.data(data),
 		.clk(clk),
-		.wr(wr),
-		.rd(rd)
+		.address(addr[1]),
+		.data(data[1]),
+		.wr(wr[1]),
+		.rd(rd[1])
 		);
 
 	Timer tmr(
 		.clk(clk),
-		.wr(wr),
-		.rd(rd),
-		.addr(addr),
-		.data(data),
+		.addr(addr[0]),
+		.data(data[0]),
+		.wr(wr[0]),
+		.rd(rd[0]),
 		.irq(tmrirq)
 		);
 	
 	Interrupt intr(
 		.clk(clk),
-		.rd(rd),
-		.wr(wr),
-		.addr(addr),
-		.data(data),
+		.addr(addr[0]),
+		.data(data[0]),
+		.wr(wr[0]),
+		.rd(rd[0]),
 		.vblank(vblankirq),
 		.lcdc(lcdcirq),
 		.tovf(tmrirq),
@@ -255,90 +283,10 @@ module CoreTop(
 	
 	Soundcore sound(
 		.core_clk(clk),
-		.rd(rd),
-		.wr(wr),
-		.addr(addr),
-		.data(data),
+		.addr(addr[0]),
+		.data(data[0]),
+		.rd(rd[0]),
+		.wr(wr[0]),
 		.snd_data_l(soundl),
 		.snd_data_r(soundr));
 endmodule
-
-`ifdef verilator
-`else
-module TestBench();
-	reg clk = 1;
-	wire [15:0] addr;
-	wire [7:0] data;
-	wire wr, rd;
-	
-	wire irq, tmrirq;
-	wire [7:0] jaddr;
-	
-	wire [7:0] leds;
-	wire [7:0] switches;
-	
-	always #62 clk <= ~clk;
-	GBZ80Core core(
-		.clk(clk),
-		.busaddress(addr),
-		.busdata(data),
-		.buswr(wr),
-		.busrd(rd),
-		.irq(irq),
-		.jaddr(jaddr));
-	
-	ROM rom(
-		.clk(clk),
-		.address(addr),
-		.data(data),
-		.wr(wr),
-		.rd(rd));
-	
-	InternalRAM ram(
-		.address(addr),
-		.data(data),
-		.clk(clk),
-		.wr(wr),
-		.rd(rd));
-
-	wire serio;
-	UART uart(
-		.addr(addr),
-		.data(data),
-		.clk(clk),
-		.wr(wr),
-		.rd(rd),
-		.serial(serio));
-	
-	Timer tmr(
-		.clk(clk),
-		.wr(wr),
-		.rd(rd),
-		.addr(addr),
-		.data(data),
-		.irq(tmrirq));
-	
-	Interrupt intr(
-		.clk(clk),
-		.rd(rd),
-		.wr(wr),
-		.addr(addr),
-		.data(data),
-		.vblank(0),
-		.lcdc(0),
-		.tovf(tmrirq),
-		.serial(0),
-		.buttons(0),
-		.master(irq),
-		.jaddr(jaddr));
-	
-	Switches sw(
-		.clk(clk),
-		.address(addr),
-		.data(data),
-		.wr(wr),
-		.rd(rd),
-		.switches(switches),
-		.ledout(leds));
-endmodule
-`endif