X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/c87db60a8f262ec834a46432e5d7b9a4faf09e09..dadf7990cbca24581bbb3c036df717dd59bdea41:/System.v diff --git a/System.v b/System.v index dec02b8..8bc14e9 100644 --- a/System.v +++ b/System.v @@ -22,7 +22,7 @@ module InternalRAM( input wr, rd); // synthesis attribute ram_style of reg is block - reg [7:0] ram [2047:0]; + reg [7:0] ram [8191:0]; wire decode = address[15:13] == 3'b110; reg [7:0] odata; @@ -31,11 +31,11 @@ module InternalRAM( always @(negedge clk) begin - if (decode) - begin - if (wr) - ram[address[10:0]] <= data; - odata <= ram[address[10:0]]; + if (decode) // This has to go this way. The only way XST knows how to do + begin // block ram is chip select, write enable, and always + if (wr) // reading. "else if rd" does not cut it ... + ram[address[12:0]] <= data; + odata <= ram[address[12:0]]; end end endmodule