X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/c87db60a8f262ec834a46432e5d7b9a4faf09e09..3785d05a183aa8de851f361432c5da2cc8f11c16:/System.v

diff --git a/System.v b/System.v
index dec02b8..8b8d613 100644
--- a/System.v
+++ b/System.v
@@ -22,7 +22,7 @@ module InternalRAM(
 	input wr, rd);
 	
 	// synthesis attribute ram_style of reg is block
-	reg [7:0] ram [2047:0];
+	reg [7:0] ram [8191:0];
 	
 	wire decode = address[15:13] == 3'b110;
 	reg [7:0] odata;
@@ -31,11 +31,11 @@ module InternalRAM(
 	
 	always @(negedge clk)
 	begin
-		if (decode)
-		begin
-			if (wr)
-				ram[address[10:0]] <= data;
-			odata <= ram[address[10:0]];
+		if (decode)	// This has to go this way. The only way XST knows how to do
+		begin				// block ram is chip select, write enable, and always
+			if (wr)		// reading. "else if rd" does not cut it ...
+				ram[address[12:0]] <= data;
+			odata <= ram[address[12:0]];
 		end
 	end
 endmodule
@@ -70,9 +70,7 @@ module CoreTop(
 	output wire [3:0] digits,
 	output wire [7:0] seven);
 	
-	wire clk;
-	//IBUFG ibuf (.O(clk), .I(iclk));
-	
+	wire clk;	
 	CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
 
 	wire [15:0] addr;	
@@ -111,7 +109,7 @@ module CoreTop(
 		.switches(switches)
 		);
 
-	UART nouart (
+	UART nouart (	/* no u */
     .clk(clk), 
     .wr(wr), 
     .rd(rd), 
@@ -126,10 +124,34 @@ module CoreTop(
 		.clk(clk),
 		.wr(wr),
 		.rd(rd));
+
+	wire irq, tmrirq;
+	wire [7:0] jaddr;
+	Timer tmr(
+		.clk(clk),
+		.wr(wr),
+		.rd(rd),
+		.addr(addr),
+		.data(data),
+		.irq(tmrirq));
+	
+	Interrupt intr(
+		.clk(clk),
+		.rd(rd),
+		.wr(wr),
+		.addr(addr),
+		.data(data),
+		.vblank(0),
+		.lcdc(0),
+		.tovf(tmrirq),
+		.serial(0),
+		.buttons(0),
+		.master(irq),
+		.jaddr(jaddr));
 endmodule
 
 module TestBench();
-	reg clk = 0;
+	reg clk = 1;
 	wire [15:0] addr;
 	wire [7:0] data;
 	wire wr, rd;
@@ -168,6 +190,30 @@ module TestBench();
 		.rd(rd),
 		.serial(serio));
 	
+	wire irq, tmrirq;
+	wire [7:0] jaddr;
+	Timer tmr(
+		.clk(clk),
+		.wr(wr),
+		.rd(rd),
+		.addr(addr),
+		.data(data),
+		.irq(tmrirq));
+	
+	Interrupt intr(
+		.clk(clk),
+		.rd(rd),
+		.wr(wr),
+		.addr(addr),
+		.data(data),
+		.vblank(0),
+		.lcdc(0),
+		.tovf(tmrirq),
+		.serial(0),
+		.buttons(0),
+		.master(irq),
+		.jaddr(jaddr));
+	
 //	Switches sw(
 //		.clk(clk),
 //		.address(addr),