X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/c279b66691509cfc4445a568dab29a3282f03f3f..2854e3991ab66f6fb954aba96caf7875d049431e:/System.v?ds=sidebyside diff --git a/System.v b/System.v index caa6ae3..1872e51 100644 --- a/System.v +++ b/System.v @@ -6,16 +6,33 @@ module ROM( input clk, input wr, rd); + reg [7:0] odata; + + // synthesis attribute ram_style of rom is block reg [7:0] rom [1023:0]; initial $readmemh("rom.hex", rom); wire decode = address[15:13] == 0; - wire [7:0] odata = rom[address[10:0]]; + always @(posedge clk) + odata <= rom[address[10:0]]; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; +endmodule + +module BootstrapROM( + input [15:0] address, + inout [7:0] data, + input clk, + input wr, rd); + + reg [7:0] brom [255:0]; + initial $readmemh("bootstrap.hex", brom); + + wire decode = address[15:8] == 0; + wire [7:0] odata = brom[address[7:0]]; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - //assign data = rd ? odata : 8'bzzzzzzzz; endmodule -module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */ +module MiniRAM( input [15:0] address, inout [7:0] data, input clk, @@ -27,7 +44,7 @@ module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */ reg [7:0] odata; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - always @(negedge clk) + always @(posedge clk) begin if (decode) // This has to go this way. The only way XST knows how to do begin // block ram is chip select, write enable, and always @@ -51,7 +68,7 @@ module InternalRAM( reg [7:0] odata; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - always @(negedge clk) + always @(posedge clk) begin if (decode) // This has to go this way. The only way XST knows how to do begin // block ram is chip select, write enable, and always @@ -74,7 +91,7 @@ module Switches( reg [7:0] odata; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - always @(negedge clk) + always @(posedge clk) begin if (decode && rd) odata <= switches; @@ -83,7 +100,16 @@ module Switches( end endmodule +`ifdef isim +module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk); +endmodule +`endif + module CoreTop( +`ifdef isim + output reg vgaclk = 0, + output reg clk = 0, +`else input xtal, input [7:0] switches, input [3:0] buttons, @@ -91,18 +117,34 @@ module CoreTop( output serio, output wire [3:0] digits, output wire [7:0] seven, +`endif output wire hs, vs, output wire [2:0] r, g, - output wire [1:0] b); + output wire [1:0] b, + output wire soundl, soundr); + +`ifdef isim + always #62 clk <= ~clk; + always #100 vgaclk <= ~vgaclk; + + Dumpable dump(r,g,b,hs,vs,vgaclk); + wire [7:0] leds; + wire serio; + wire [3:0] digits; + wire [7:0] seven; + wire [7:0] switches = 8'b0; + wire [3:0] buttons = 4'b0; +`else wire xtalb, clk, vgaclk; IBUFG iclkbuf(.O(xtalb), .I(xtal)); CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk)); pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk)); - - wire [15:0] addr; - wire [7:0] data; - wire wr, rd; +`endif + + wire [15:0] addr [1:0]; + wire [7:0] data [1:0]; + wire wr [1:0], rd [1:0]; wire irq, tmrirq, lcdcirq, vblankirq; wire [7:0] jaddr; @@ -110,31 +152,42 @@ module CoreTop( GBZ80Core core( .clk(clk), - .busaddress(addr), - .busdata(data), - .buswr(wr), - .busrd(rd), + .bus0address(addr[0]), + .bus0data(data[0]), + .bus0wr(wr[0]), + .bus0rd(rd[0]), + .bus1address(addr[1]), + .bus1data(data[1]), + .bus1wr(wr[1]), + .bus1rd(rd[1]), .irq(irq), .jaddr(jaddr), .state(state)); + BootstrapROM brom( + .address(addr[1]), + .data(data[1]), + .clk(clk), + .wr(wr[1]), + .rd(rd[1])); + ROM rom( - .address(addr), - .data(data), + .address(addr[0]), + .data(data[0]), .clk(clk), - .wr(wr), - .rd(rd)); + .wr(wr[0]), + .rd(rd[0])); wire lcdhs, lcdvs, lcdclk; wire [2:0] lcdr, lcdg; wire [1:0] lcdb; LCDC lcdc( - .addr(addr), - .data(data), .clk(clk), - .wr(wr), - .rd(rd), + .addr(addr[0]), + .data(data[0]), + .wr(wr[0]), + .rd(rd[0]), .lcdcirq(lcdcirq), .vblankirq(vblankirq), .lcdclk(lcdclk), @@ -159,8 +212,8 @@ module CoreTop( .vgab(b)); AddrMon amon( - .addr(addr), .clk(clk), + .addr(addr[0]), .digit(digits), .out(seven), .freeze(buttons[0]), @@ -171,137 +224,69 @@ module CoreTop( 4'b0100) ); Switches sw( - .address(addr), - .data(data), .clk(clk), - .wr(wr), - .rd(rd), + .address(addr[0]), + .data(data[0]), + .wr(wr[0]), + .rd(rd[0]), .ledout(leds), .switches(switches) ); UART nouart ( /* no u */ - .clk(clk), - .wr(wr), - .rd(rd), - .addr(addr), - .data(data), + .clk(clk), + .addr(addr[0]), + .data(data[0]), + .wr(wr[0]), + .rd(rd[0]), .serial(serio) ); InternalRAM ram( - .address(addr), - .data(data), .clk(clk), - .wr(wr), - .rd(rd) + .address(addr[0]), + .data(data[0]), + .wr(wr[0]), + .rd(rd[0]) ); MiniRAM mram( - .address(addr), - .data(data), .clk(clk), - .wr(wr), - .rd(rd) + .address(addr[1]), + .data(data[1]), + .wr(wr[1]), + .rd(rd[1]) ); Timer tmr( .clk(clk), - .wr(wr), - .rd(rd), - .addr(addr), - .data(data), + .addr(addr[0]), + .data(data[0]), + .wr(wr[0]), + .rd(rd[0]), .irq(tmrirq) ); Interrupt intr( .clk(clk), - .rd(rd), - .wr(wr), - .addr(addr), - .data(data), + .addr(addr[0]), + .data(data[0]), + .wr(wr[0]), + .rd(rd[0]), .vblank(vblankirq), .lcdc(lcdcirq), .tovf(tmrirq), - .serial(0), - .buttons(0), - .master(irq), - .jaddr(jaddr)); -endmodule - -module TestBench(); - reg clk = 1; - wire [15:0] addr; - wire [7:0] data; - wire wr, rd; - - wire irq, tmrirq; - wire [7:0] jaddr; - - wire [7:0] leds; - wire [7:0] switches; - - always #62 clk <= ~clk; - GBZ80Core core( - .clk(clk), - .busaddress(addr), - .busdata(data), - .buswr(wr), - .busrd(rd), - .irq(irq), - .jaddr(jaddr)); - - ROM rom( - .clk(clk), - .address(addr), - .data(data), - .wr(wr), - .rd(rd)); - - InternalRAM ram( - .address(addr), - .data(data), - .clk(clk), - .wr(wr), - .rd(rd)); - - wire serio; - UART uart( - .addr(addr), - .data(data), - .clk(clk), - .wr(wr), - .rd(rd), - .serial(serio)); - - Timer tmr( - .clk(clk), - .wr(wr), - .rd(rd), - .addr(addr), - .data(data), - .irq(tmrirq)); - - Interrupt intr( - .clk(clk), - .rd(rd), - .wr(wr), - .addr(addr), - .data(data), - .vblank(0), - .lcdc(0), - .tovf(tmrirq), - .serial(0), - .buttons(0), + .serial(1'b0), + .buttons(1'b0), .master(irq), .jaddr(jaddr)); - Switches sw( - .clk(clk), - .address(addr), - .data(data), - .wr(wr), - .rd(rd), - .switches(switches), - .ledout(leds)); + Soundcore sound( + .core_clk(clk), + .addr(addr[0]), + .data(data[0]), + .rd(rd[0]), + .wr(wr[0]), + .snd_data_l(soundl), + .snd_data_r(soundr)); endmodule