X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/b85870e0cf3c61677a430559c9621a665a8bab6d..634ce02ca41547deda6e98f0e16a81f849bb130c:/GBZ80Core.v?ds=sidebyside

diff --git a/GBZ80Core.v b/GBZ80Core.v
index e5a7d35..fa9ed0b 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -26,6 +26,8 @@
 `define INSN_LD_HL_reg		8'b01110xxx
 `define INSN_LD_reg_HL		8'b01xxx110
 `define INSN_LD_reg_reg		8'b01xxxxxx
+`define INSN_LD_reg_imm16	8'b00xx0001
+`define INSN_LD_SP_HL		8'b11111001
 `define INSN_reg_A		3'b111
 `define INSN_reg_B		3'b000
 `define INSN_reg_C		3'b001
@@ -34,7 +36,10 @@
 `define INSN_reg_H		3'b100
 `define INSN_reg_L		3'b101
 `define INSN_reg_dHL	3'b110
-
+`define INSN_reg16_BC	2'b00
+`define INSN_reg16_DE	2'b01
+`define INSN_reg16_HL	2'b10
+`define INSN_reg16_SP	2'b11
 module GBZ80Core(
 	input clk,
 	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
@@ -130,13 +135,42 @@ module GBZ80Core(
 				endcase
 			end
 			`INSN_HALT: begin
-				/* XXX UNIMP */
+				`EXEC_NEWCYCLE;
+				/* XXX Interrupts needed for HALT. */
 			end
 			`INSN_LD_HL_reg: begin
-				/* XXX UNIMP */
+				case (cycle)
+				0:	begin
+						case (opcode[2:0])
+						`INSN_reg_A:	begin wdata <= registers[`REG_A]; end
+						`INSN_reg_B:	begin wdata <= registers[`REG_B]; end
+						`INSN_reg_C:	begin wdata <= registers[`REG_C]; end
+						`INSN_reg_D:	begin wdata <= registers[`REG_D]; end
+						`INSN_reg_E:	begin wdata <= registers[`REG_E]; end
+						`INSN_reg_H:	begin wdata <= registers[`REG_H]; end
+						`INSN_reg_L:	begin wdata <= registers[`REG_L]; end
+						endcase
+						address <= {registers[`REG_H], registers[`REG_L]};
+						wr <= 1; rd <= 0;
+					end
+				1:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEWCYCLE;
+					end
+				endcase
 			end
 			`INSN_LD_reg_HL: begin
-				/* XXX UNIMP */
+				case(cycle)
+				0: begin
+						address <= {registers[`REG_H], registers[`REG_L]};
+						wr <= 0; rd <= 1;
+					end
+				1: begin
+						tmp <= rdata;
+						`EXEC_INC_PC;
+						`EXEC_NEWCYCLE;
+					end
+				endcase
 			end
 			`INSN_LD_reg_reg: begin
 				`EXEC_INC_PC;
@@ -151,46 +185,129 @@ module GBZ80Core(
 				`INSN_reg_L:	begin tmp <= registers[`REG_L]; end
 				endcase
 			end
+			`INSN_LD_reg_imm16: begin
+				`EXEC_INC_PC;
+				case (cycle)
+				0:	begin
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				1:	begin
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				2: begin `EXEC_NEWCYCLE; end
+				endcase
+			end
+			`INSN_LD_SP_HL: begin
+				case (cycle)
+				0:	begin
+						rd <= 0;
+						address <= 16'bxxxxxxxxxxxxxxxx;
+						tmp <= registers[`REG_H];
+					end
+				1:	begin
+						`EXEC_NEWCYCLE;
+						`EXEC_INC_PC;
+						tmp <= registers[`REG_L];
+					end
+				endcase
+			end
+			default:
+				$stop;
 			endcase
 			state <= `STATE_WRITEBACK;
 		end
 		`STATE_WRITEBACK: begin
 			casex (opcode)
-				`INSN_LD_reg_imm8:
-					case (cycle)
-					0: cycle <= 1;
-					1: case (opcode[5:3])
-						`INSN_reg_A:	begin registers[`REG_A] <= rdata; cycle <= 0; end
-						`INSN_reg_B:	begin registers[`REG_B] <= rdata; cycle <= 0; end
-						`INSN_reg_C:	begin registers[`REG_C] <= rdata; cycle <= 0; end
-						`INSN_reg_D:	begin registers[`REG_D] <= rdata; cycle <= 0; end
-						`INSN_reg_E:	begin registers[`REG_E] <= rdata; cycle <= 0; end
-						`INSN_reg_H:	begin registers[`REG_H] <= rdata; cycle <= 0; end
-						`INSN_reg_L:	begin registers[`REG_L] <= rdata; cycle <= 0; end
-						`INSN_reg_dHL:	cycle <= 2;
-						endcase
-					2: cycle <= 0;
-					endcase
-				`INSN_HALT: begin
-					/* XXX UNIMP */
-				end
-				`INSN_LD_HL_reg: begin
-					/* XXX UNIMP */
-				end
-				`INSN_LD_reg_HL: begin
-					/* XXX UNIMP */
-				end
-				`INSN_LD_reg_reg: begin
-					case (opcode[5:3])
-					`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
-					`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
-					`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
-					`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
-					`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
-					`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
-					`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
+			`INSN_LD_reg_imm8:
+				case (cycle)
+				0: cycle <= 1;
+				1: case (opcode[5:3])
+					`INSN_reg_A:	begin registers[`REG_A] <= rdata; cycle <= 0; end
+					`INSN_reg_B:	begin registers[`REG_B] <= rdata; cycle <= 0; end
+					`INSN_reg_C:	begin registers[`REG_C] <= rdata; cycle <= 0; end
+					`INSN_reg_D:	begin registers[`REG_D] <= rdata; cycle <= 0; end
+					`INSN_reg_E:	begin registers[`REG_E] <= rdata; cycle <= 0; end
+					`INSN_reg_H:	begin registers[`REG_H] <= rdata; cycle <= 0; end
+					`INSN_reg_L:	begin registers[`REG_L] <= rdata; cycle <= 0; end
+					`INSN_reg_dHL:	cycle <= 2;
 					endcase
-				end
+				2: cycle <= 0;
+				endcase
+			`INSN_HALT: begin
+				/* Nothing needs happen here. */
+				/* XXX Interrupts needed for HALT. */
+			end
+			`INSN_LD_HL_reg: begin
+				case (cycle)
+				0: cycle <= 1;
+				1: cycle <= 0;
+				endcase
+			end
+			`INSN_LD_reg_HL: begin
+				case (cycle)
+				0:	cycle <= 1;
+				1:	begin
+						case (opcode[5:3])
+						`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
+						`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
+						`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
+						`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
+						`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
+						`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
+						`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
+						endcase
+						cycle <= 0;
+					end
+				endcase
+			end
+			`INSN_LD_reg_reg: begin
+				case (opcode[5:3])
+				`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
+				`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
+				`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
+				`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
+				`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
+				`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
+				`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
+				endcase
+			end
+			`INSN_LD_reg_imm16: begin
+				case (cycle)
+				0:	cycle <= 1;
+				1:	begin
+						case (opcode[5:4])
+						`INSN_reg16_BC:	registers[`REG_C] <= rdata;
+						`INSN_reg16_DE:	registers[`REG_E] <= rdata;
+						`INSN_reg16_HL:	registers[`REG_L] <= rdata;
+						`INSN_reg16_SP:	registers[`REG_SPL] <= rdata;
+						endcase
+						cycle <= 2;
+					end
+				2: begin
+						case (opcode[5:4])
+						`INSN_reg16_BC:	registers[`REG_B] <= rdata;
+						`INSN_reg16_DE:	registers[`REG_D] <= rdata;
+						`INSN_reg16_HL:	registers[`REG_H] <= rdata;
+						`INSN_reg16_SP:	registers[`REG_SPH] <= rdata;
+						endcase
+						cycle <= 0;
+					end
+				endcase
+			end
+			`INSN_LD_SP_HL: begin
+				case (cycle)
+				0: begin
+						cycle <= 1;
+						registers[`REG_SPH] <= tmp;
+					end
+				1: begin
+						cycle <= 0;
+						registers[`REG_SPL] <= tmp;
+					end
+				endcase
+			end
 			endcase
 			state <= `STATE_FETCH;
 		end