X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/b4f3ac35e69b7d5adf57959902abe2a104b42f4f..207251ed32471a6c5fba766d7f73e92a8d86b7cf:/LCDC.v diff --git a/LCDC.v b/LCDC.v index 7b402e4..c550288 100644 --- a/LCDC.v +++ b/LCDC.v @@ -21,13 +21,17 @@ module LCDC( output wire lcdclk, lcdvs, lcdhs, output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb); + /***** Bus latches *****/ + reg rdlatch = 0; + reg [15:0] addrlatch = 0; + /***** Needed prototypes *****/ wire [1:0] pixdata; /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/ reg clk4 = 0; always @(posedge clk) - clk4 = ~clk4; + clk4 <= ~clk4; /***** LCD control registers *****/ reg [7:0] rLCDC = 8'h00; @@ -131,8 +135,8 @@ module LCDC( * Tile data from 8000-8FFF or 8800-97FF * Background tile maps 9800-9BFF or 9C00-9FFF */ - reg [7:0] tiledatahigh [3071:0]; - reg [7:0] tiledatalow [3071:0]; + reg [7:0] tiledatahigh [6143:0]; + reg [7:0] tiledatalow [6143:0]; reg [7:0] bgmap1 [1023:0]; reg [7:0] bgmap2 [1023:0]; @@ -142,26 +146,35 @@ module LCDC( // The new tile data is latched and ready when vxpos[2:0] is 3'b000! wire [7:0] vxpos_ = vxpos + 1; wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]}; - reg [7:0] tileno; - wire [10:0] tileaddr = {tileno, vypos[2:0]}; + reg [7:0] tileno1; + reg [7:0] tileno2; + wire [7:0] tileno = rLCDC[3] ? tileno2 : tileno1; + wire [11:0] tileaddr = + {(rLCDC[4] ? {1'b0,tileno} : (9'b100000000 + {tileno[7],tileno})), + vypos[2:0]}; reg [7:0] tilehigh, tilelow; wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]}; - assign pixdata = {rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]}; + assign pixdata = 2'b11-{rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]}; wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF); wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF); + wire decode_bgmap2 = (addr >= 16'h9C00) && (addr <= 16'h9FFF); wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0]; wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1]; - always @(negedge clk) + always @(posedge clk) + begin if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin - tileno <= bgmap1[bgmapaddr_in]; + tileno1 <= bgmap1[bgmapaddr_in]; if (wr && decode_bgmap1 && ~vraminuse) bgmap1[bgmapaddr_in] <= data; end - - always @(negedge clk) + if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap2) begin + tileno2 <= bgmap2[bgmapaddr_in]; + if (wr && decode_bgmap2 && ~vraminuse) + bgmap2[bgmapaddr_in] <= data; + end if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin tilehigh <= tiledatahigh[tileaddr_in]; tilelow <= tiledatalow[tileaddr_in]; @@ -170,28 +183,31 @@ module LCDC( if (wr && ~addr[0] && decode_tiledata && ~vraminuse) tiledatalow[tileaddr_in] <= data; end + end /***** Bus interface *****/ - assign data = rd ? - ((addr == `ADDR_LCDC) ? rLCDC : - (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} : - (addr == `ADDR_SCY) ? rSCY : - (addr == `ADDR_SCX) ? rSCX : - (addr == `ADDR_LY) ? posy : - (addr == `ADDR_LYC) ? rLYC : - (addr == `ADDR_BGP) ? rBGP : - (addr == `ADDR_OBP0) ? rOBP0 : - (addr == `ADDR_OBP1) ? rOBP1 : - (addr == `ADDR_WY) ? rWY : - (addr == `ADDR_WX) ? rWX : - (decode_tiledata && addr[0]) ? tilehigh : - (decode_tiledata && ~addr[0]) ? tilelow : + assign data = rdlatch ? + ((addrlatch == `ADDR_LCDC) ? rLCDC : + (addrlatch == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} : + (addrlatch == `ADDR_SCY) ? rSCY : + (addrlatch == `ADDR_SCX) ? rSCX : + (addrlatch == `ADDR_LY) ? posy : + (addrlatch == `ADDR_LYC) ? rLYC : + (addrlatch == `ADDR_BGP) ? rBGP : + (addrlatch == `ADDR_OBP0) ? rOBP0 : + (addrlatch == `ADDR_OBP1) ? rOBP1 : + (addrlatch == `ADDR_WY) ? rWY : + (addrlatch == `ADDR_WX) ? rWX : + (decode_tiledata && addrlatch[0]) ? tilehigh : + (decode_tiledata && ~addrlatch[0]) ? tilelow : (decode_bgmap1) ? tileno : 8'bzzzzzzzz) : 8'bzzzzzzzz; - always @(negedge clk) + always @(posedge clk) begin + rdlatch <= rd; + addrlatch <= addr; if (wr) case (addr) `ADDR_LCDC: rLCDC <= data;