X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/b057a5d6e6db6db06ae33703ca72cd235eec91d6..c231e6fbb4876ff512be460e60451c77c7caab69:/System.v

diff --git a/System.v b/System.v
index 37ca872..f89b2a6 100644
--- a/System.v
+++ b/System.v
@@ -81,6 +81,7 @@ module CellularRAM(
 	inout [7:0] data,
 	input wr, rd,
 	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+	output wire st_nCE, st_nRST,
 	output wire [22:0] cr_A,
 	inout [15:0] cr_DQ);
 	
@@ -88,6 +89,7 @@ module CellularRAM(
 	parameter ADDR_PROGADDRM = 16'hFF61;
 	parameter ADDR_PROGADDRL = 16'hFF62;
 	parameter ADDR_PROGDATA = 16'hFF63;
+	parameter ADDR_PROGFLASH = 16'hFF65;
 	parameter ADDR_MBC = 16'hFF64;
 	
 	reg rdlatch = 0, wrlatch = 0;
@@ -102,25 +104,28 @@ module CellularRAM(
 						// low 7 bits are the MBC that we are emulating
 	
 	assign cr_nADV = 0;	/* Addresses are always valid! :D */
-	assign cr_nCE = 0;	/* The chip is enabled */
+	assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH);	/* The chip is enabled */
 	assign cr_nLB = 0;	/* Lower byte is enabled */
 	assign cr_nUB = 0;	/* Upper byte is enabled */
 	assign cr_CRE = 0;	/* Data writes, not config */
 	assign cr_CLK = 0;	/* Clock? I think not! */
 	
-	wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
+	assign st_nRST = 1;	/* Keep the strataflash out of reset. */
+	assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
+	
+	wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);
 	
 	reg [3:0] rambank = 0;
 	reg [8:0] rombank = 1;
 	
 	assign cr_nOE = decode ? ~rdlatch : 1;
-	assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1;
+	assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
 	
 	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
 	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
 			(addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
 			(addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
-			(addrlatch == ADDR_PROGDATA) ? progaddr :
+			((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :
 			23'b0;
 	
 	always @(posedge clk) begin
@@ -132,6 +137,10 @@ module CellularRAM(
 					progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
 					{progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
 				end
+		ADDR_PROGFLASH:	if (rd || wr) begin
+					progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
+					{progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
+				end
 		ADDR_MBC:	begin
 					mbc_emul <= data;
 					rambank <= 0;
@@ -229,7 +238,7 @@ module CoreTop(
 	input serin,
 	output wire [3:0] digits,
 	output wire [7:0] seven,
-	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,
 	output wire [22:0] cr_A,
 	inout [15:0] cr_DQ,
 	input ps2c, ps2d,
@@ -314,7 +323,9 @@ module CoreTop(
 		.cr_nUB(cr_nUB),
 		.cr_CLK(cr_CLK),
 		.cr_A(cr_A),
-		.cr_DQ(cr_DQ));
+		.cr_DQ(cr_DQ),
+		.st_nCE(st_nCE),
+		.st_nRST(st_nRST));
 `endif
 	
 	wire lcdhs, lcdvs, lcdclk;