X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/b057a5d6e6db6db06ae33703ca72cd235eec91d6..4c90390a786b738c0dc0b8d55e7cc2d857f625de:/core/GBZ80Core.v

diff --git a/core/GBZ80Core.v b/core/GBZ80Core.v
index 053df4a..b5a502c 100644
--- a/core/GBZ80Core.v
+++ b/core/GBZ80Core.v
@@ -40,46 +40,9 @@
 `define STATE_EXECUTE		2'h2
 `define STATE_WRITEBACK		2'h3
 
-`define INSN_LD_reg_imm8	9'b000xxx110
-`define INSN_HALT		9'b001110110
-`define INSN_LD_HL_reg		9'b001110xxx
-`define INSN_LD_reg_HL		9'b001xxx110
-`define INSN_LD_reg_reg		9'b001xxxxxx
-`define INSN_LD_reg_imm16	9'b000xx0001
-`define INSN_LD_SP_HL		9'b011111001
-`define INSN_PUSH_reg		9'b011xx0101
-`define INSN_POP_reg		9'b011xx0001
-`define INSN_LDH_AC		9'b0111x0010	// Either LDH A,(C) or LDH (C),A
-`define INSN_LDx_AHL		9'b0001xx010	// LDD/LDI A,(HL) / (HL),A
-`define INSN_ALU8		9'b010xxxxxx	// 10 xxx yyy
-`define INSN_ALU8IMM		9'b011xxx110
-`define INSN_NOP		9'b000000000
-`define INSN_RST		9'b011xxx111
-`define INSN_RET		9'b0110x1001	// 1 = RETI, 0 = RET
-`define INSN_RETCC		9'b0110xx000
-`define INSN_CALL		9'b011001101
-`define INSN_CALLCC		9'b0110xx100	// Not that call/cc.
-`define INSN_JP_imm		9'b011000011
-`define INSN_JPCC_imm		9'b0110xx010
-`define INSN_ALU_A		9'b000xxx111
-`define INSN_JP_HL		9'b011101001
-`define INSN_JR_imm		9'b000011000
-`define INSN_JRCC_imm		9'b0001xx000
-`define INSN_INCDEC16		9'b000xxx011
 `define INSN_VOP_INTR		9'b011111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
-`define INSN_DI			9'b011110011
-`define INSN_EI			9'b011111011
-`define INSN_INCDEC_HL		9'b00011010x
-`define INSN_INCDEC_reg8	9'b000xxx10x
-`define INSN_LD8M_A		9'b0111x0000	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
-`define INSN_LD16M_A		9'b0111x1010	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
-`define INSN_LDBCDE_A		9'b0000xx010
-`define INSN_TWO_BYTE		9'b011001011    // prefix for two-byte opqodes
-`define INSN_ALU_EXT		9'b100xxxxxx
-`define INSN_BIT		9'b101xxxxxx
 `define INSN_RES		9'b110xxxxxx
 `define INSN_SET		9'b111xxxxxx
-`define INSN_ADD_HL		9'b000xx1001
 
 `define INSN_cc_NZ		2'b00
 `define INSN_cc_Z		2'b01
@@ -110,14 +73,6 @@
 `define INSN_alu_XOR		3'b101
 `define INSN_alu_OR		3'b110
 `define INSN_alu_CP		3'b111		// Oh lawd, is dat some CP?
-`define INSN_alu_RLCA		3'b000
-`define INSN_alu_RRCA		3'b001
-`define INSN_alu_RLA		3'b010
-`define INSN_alu_RRA		3'b011
-`define INSN_alu_DAA		3'b100
-`define INSN_alu_CPL		3'b101
-`define INSN_alu_SCF		3'b110
-`define INSN_alu_CCF		3'b111
 `define INSN_alu_RLC		3'b000
 `define INSN_alu_RRC		3'b001
 `define INSN_alu_RL		3'b010
@@ -131,18 +86,13 @@
 `define EXEC_NEXTADDR_PCINC	address <= `_PC + 1;
 `define EXEC_NEWCYCLE		begin newcycle <= 1; rd <= 1; wr <= 0; end
 `define EXEC_NEWCYCLE_TWOBYTE	begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
-`ifdef verilator
+`ifdef isim
 	`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end
 	`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end
 `else
-	`ifdef isim
-		`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end
-		`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end
-	`else
-/* Work around XST's retarded bugs :\ */
-		`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
-		`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end
-	`endif
+	/* Work around XST's retarded bugs :\ */
+	`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
+	`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end
 `endif
 
 module GBZ80Core(
@@ -196,64 +146,9 @@ module GBZ80Core(
 
 	reg ie, iedelay;
 
-	wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
-	wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
-	wire [7:0] alu_res;
-	wire [3:0] f_res;
-
-	assign rlc   = {tmp[6:0],tmp[7]};
-	assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
-			,2'b0,
-			tmp[7]};
-
-	assign rrc   = {tmp[0],tmp[7:1]};
-	assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
-			2'b0,
-			tmp[0]};
-
-	assign rl    = {tmp[6:0],`_F[4]};
-	assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
-			2'b0,
-			tmp[7]};
-
-	assign rr    = {`_F[4],tmp[7:1]};
-	assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
-			2'b0,
-			tmp[0]};
-
-	assign sla   = {tmp[6:0],1'b0};
-	assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
-			2'b0,
-			tmp[7]};
-
-	assign sra   = {tmp[7],tmp[7:1]};
-//	assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
-
-	assign swap  = {tmp[3:0],tmp[7:4]};
-	assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
-			3'b0};
-
-	assign srl   = {1'b0,tmp[7:1]};
-	assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
-			2'b0,
-			tmp[0]};
-	assign sraf  = srlf;
-
-	/*  Y U Q  */
-	assign {alu_res,f_res} =
-		opcode[5] ? (
-			opcode[4] ? (
-				opcode[3] ? {srl,srlf} : {swap,swapf}
-			) : (
-				opcode[3] ? {sra,sraf} : {sla,slaf}
-			)
-		) : (
-			opcode[4] ? (
-				opcode[3] ? {rr,rrf} : {rl,rlf}
-			) : (
-				opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
-			)
-		);
+`define LOCALWIRES
+`include "allinsns.v"
+`undef LOCALWIRES
 
 	initial begin
 		`_A <= 0;