X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/a8f4468d0cd6910eba8031e21038d76857a2c107..58f7754ae52df7679f3224d7e77f6312e45ba4bb:/System.v diff --git a/System.v b/System.v index ebc9be4..b1d4c3d 100644 --- a/System.v +++ b/System.v @@ -28,13 +28,16 @@ module BootstrapROM( input wr, rd); reg rdlatch = 0; + reg [7:0] addrlatch = 0; reg [7:0] brom [255:0]; initial $readmemh("bootstrap.hex", brom); wire decode = address[15:8] == 0; - wire [7:0] odata = brom[address[7:0]]; - always @(posedge clk) + wire [7:0] odata = brom[addrlatch]; + always @(posedge clk) begin rdlatch <= rd && decode; + addrlatch <= address[7:0]; + end assign data = rdlatch ? odata : 8'bzzzzzzzz; endmodule @@ -259,11 +262,11 @@ module CoreTop( .data(data[0]), .clk(clk), .wr(wr[0]), - .rd(rd[0]) + .rd(rd[0]), .cr_nADV(cr_nADV), .cr_nCE(cr_nCE), .cr_nOE(cr_nOE), - .cr_nWR(cr_nWE), + .cr_nWE(cr_nWE), .cr_CRE(cr_CRE), .cr_nLB(cr_nLB), .cr_nUB(cr_nUB),