X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/a8f4468d0cd6910eba8031e21038d76857a2c107..1eefdc8e89a69963b1c1a084fe4ecec844997293:/System.v

diff --git a/System.v b/System.v
index ebc9be4..62683d3 100644
--- a/System.v
+++ b/System.v
@@ -28,13 +28,22 @@ module BootstrapROM(
 	input wr, rd);
 
 	reg rdlatch = 0;
-	reg [7:0] brom [255:0];
-	initial $readmemh("bootstrap.hex", brom);
+	reg [7:0] addrlatch = 0;
+	reg romno = 0, romnotmp = 0;
+	reg [7:0] brom0 [255:0];
+	reg [7:0] brom1 [255:0];
+	
+	initial $readmemh("fpgaboot.hex", brom0);
+	initial $readmemh("gbboot.hex", brom1);
 
 	wire decode = address[15:8] == 0;
-	wire [7:0] odata = brom[address[7:0]];
-	always @(posedge clk)
+	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
+	always @(posedge clk) begin
 		rdlatch <= rd && decode;
+		addrlatch <= address[7:0];
+		if (wr && decode) romnotmp <= data[0];
+		if (rd && address == 16'h0000) romno <= romnotmp;	/* Latch when the program restarts. */
+	end
 	assign data = rdlatch ? odata : 8'bzzzzzzzz;
 endmodule
 
@@ -83,6 +92,8 @@ module CellularRAM(
 	
 	reg [7:0] progaddrh, progaddrm, progaddrl;
 	
+	reg [22:0] progaddr;
+	
 	assign cr_nADV = 0;	/* Addresses are always valid! :D */
 	assign cr_nCE = 0;	/* The chip is enabled */
 	assign cr_nLB = 0;	/* Lower byte is enabled */
@@ -98,7 +109,7 @@ module CellularRAM(
 	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
 	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
 			(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
-			(addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
+			(addrlatch == ADDR_PROGDATA) ? progaddr :
 			23'b0;
 	
 	reg [7:0] regbuf;
@@ -108,6 +119,10 @@ module CellularRAM(
 		ADDR_PROGADDRH: if (wr) progaddrh <= data;
 		ADDR_PROGADDRM: if (wr) progaddrm <= data;
 		ADDR_PROGADDRL: if (wr) progaddrl <= data;
+		ADDR_PROGDATA:	if (rd || wr) begin
+					progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]};
+					{progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} + 23'b1;
+				end
 		endcase
 		rdlatch <= rd;
 		wrlatch <= wr;
@@ -259,11 +274,11 @@ module CoreTop(
 		.data(data[0]),
 		.clk(clk),
 		.wr(wr[0]),
-		.rd(rd[0])
+		.rd(rd[0]),
 		.cr_nADV(cr_nADV),
 		.cr_nCE(cr_nCE),
 		.cr_nOE(cr_nOE),
-		.cr_nWR(cr_nWE),
+		.cr_nWE(cr_nWE),
 		.cr_CRE(cr_CRE),
 		.cr_nLB(cr_nLB),
 		.cr_nUB(cr_nUB),