X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/a85b19a7c7e7fecb4e71c41b37fb30dabaf8bd14..f26748f71f3f39de15a1c07f95c15f8c4481f452:/GBZ80Core.v diff --git a/GBZ80Core.v b/GBZ80Core.v index 1bc8f78..3cd46e3 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -36,9 +36,15 @@ `define INSN_NOP 8'b00000000 `define INSN_RST 8'b11xxx111 `define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET +`define INSN_RETCC 8'b110xx000 `define INSN_CALL 8'b11001101 +`define INSN_CALLCC 8'b110xx100 // Not that call/cc. `define INSN_JP_imm 8'b11000011 `define INSN_JPCC_imm 8'b110xx010 +`define INSN_ALU_A 8'b00xxx111 +`define INSN_JP_HL 8'b11101001 +`define INSN_JR_imm 8'b00011000 +`define INSN_JRCC_imm 8'b001xx000 `define INSN_cc_NZ 2'b00 `define INSN_cc_Z 2'b01 @@ -69,6 +75,14 @@ `define INSN_alu_XOR 3'b101 `define INSN_alu_OR 3'b110 `define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP? +`define INSN_alu_RLCA 3'b000 +`define INSN_alu_RRCA 3'b001 +`define INSN_alu_RLA 3'b010 +`define INSN_alu_RRA 3'b011 +`define INSN_alu_DAA 3'b100 +`define INSN_alu_CPL 3'b101 +`define INSN_alu_SCF 3'b110 +`define INSN_alu_CCF 3'b111 module GBZ80Core( input clk, @@ -280,7 +294,7 @@ module GBZ80Core( `INSN_stack_HL: wdata <= registers[`REG_L]; endcase end - 2: begin /* TWIDDLE OUR FUCKING THUMBS! */ end + 2: begin /* Twiddle thumbs. */ end 3: begin `EXEC_NEWCYCLE; `EXEC_INC_PC; @@ -357,6 +371,10 @@ module GBZ80Core( endcase end end + `INSN_ALU_A: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end `INSN_NOP: begin `EXEC_NEWCYCLE; `EXEC_INC_PC; @@ -383,24 +401,35 @@ module GBZ80Core( end endcase end - `INSN_RET: begin + `INSN_RET,`INSN_RETCC: begin case (cycle) 0: begin rd <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}; end - 1: begin + 1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret! + `EXEC_INC_PC; + case (opcode[4:3]) // cycle 1 is skipped if we are not retcc + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}; + end + 2: begin rd <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1; end - 2: begin /* twiddle thumbs */ end - 3: begin + 3: begin /* twiddle thumbs */ end + 4: begin `EXEC_NEWCYCLE; // do NOT increment PC! end endcase end - `INSN_CALL: begin + `INSN_CALL,`INSN_CALLCC: begin case (cycle) 0: begin `EXEC_INC_PC; @@ -414,6 +443,14 @@ module GBZ80Core( end 2: begin `EXEC_INC_PC; + if (!opcode[0]) // i.e., is callcc + /* We need to check the condition code to bail out. */ + case (opcode[4:3]) + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase end 3: begin address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1; @@ -443,13 +480,14 @@ module GBZ80Core( rd <= 1; end 2: begin + `EXEC_INC_PC; if (!opcode[0]) begin // i.e., JP cc,nn /* We need to check the condition code to bail out. */ case (opcode[4:3]) `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (!registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (!registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end endcase end end @@ -458,6 +496,33 @@ module GBZ80Core( end endcase end + `INSN_JP_HL: begin + `EXEC_NEWCYCLE; + end + `INSN_JR_imm,`INSN_JRCC_imm: begin + case (cycle) + 0: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 1: begin + `EXEC_INC_PC; + if (opcode[5]) begin // i.e., JP cc,nn + /* We need to check the condition code to bail out. */ + case (opcode[4:3]) + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase + end + end + 2: begin + `EXEC_NEWCYCLE; + end + endcase + end default: $stop; endcase @@ -622,6 +687,28 @@ module GBZ80Core( registers[`REG_F][3:0] }; end + `INSN_alu_SUB: begin + registers[`REG_A] <= + registers[`REG_A] - tmp; + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0, + /* N */ 1'b1, + /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0, + /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0, + registers[`REG_F][3:0] + }; + end + `INSN_alu_SBC: begin + registers[`REG_A] <= + registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]}); + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0, + /* N */ 1'b1, + /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0, + /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0, + registers[`REG_F][3:0] + }; + end `INSN_alu_AND: begin registers[`REG_A] <= registers[`REG_A] & tmp; @@ -649,11 +736,50 @@ module GBZ80Core( registers[`REG_F][3:0] }; end + `INSN_alu_CP: begin + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0, + /* N */ 1'b1, + /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0, + /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0, + registers[`REG_F][3:0] + }; + end default: $stop; endcase end end + `INSN_ALU_A: begin + case(opcode[5:3]) + `INSN_alu_RLCA: begin + registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]}; + registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]}; + end + `INSN_alu_RRCA: begin + registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]}; + registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]}; + end + `INSN_alu_RLA: begin + registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]}; + registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]}; + end + `INSN_alu_RRA: begin + registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]}; + registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]}; + end + `INSN_alu_CPL: begin + registers[`REG_A] <= ~registers[`REG_A]; + registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]}; + end + `INSN_alu_SCF: begin + registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]}; + end + `INSN_alu_CCF: begin + registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]}; + end + endcase + end `INSN_NOP: begin /* NOP! */ end `INSN_RST: begin case (cycle) @@ -664,20 +790,22 @@ module GBZ80Core( {registers[`REG_SPH],registers[`REG_SPL]}-2; endcase end - `INSN_RET: begin + `INSN_RET,`INSN_RETCC: begin case (cycle) - 0: begin /* type F */ end - 1: registers[`REG_PCL] <= rdata; - 2: registers[`REG_PCH] <= rdata; - 3: begin + 0: if (opcode[0]) // i.e., not RETCC + cycle <= 1; // Skip cycle 1; it gets incremented on the next round. + 1: begin /* Nothing need happen here. */ end + 2: registers[`REG_PCL] <= rdata; + 3: registers[`REG_PCH] <= rdata; + 4: begin {registers[`REG_SPH],registers[`REG_SPL]} <= {registers[`REG_SPH],registers[`REG_SPL]} + 2; - if (opcode[4]) /* RETI */ + if (opcode[4] && (opcode != `INSN_RETCC)) /* RETI */ ie <= 1; end endcase end - `INSN_CALL: begin + `INSN_CALL,`INSN_CALLCC: begin case (cycle) 0: begin /* type F */ end 1: tmp <= rdata; // tmp contains newpcl @@ -700,6 +828,19 @@ module GBZ80Core( {tmp2,tmp}; endcase end + `INSN_JP_HL: begin + {registers[`REG_PCH],registers[`REG_PCL]} <= + {registers[`REG_H],registers[`REG_L]}; + end + `INSN_JR_imm,`INSN_JRCC_imm: begin + case (cycle) + 0: begin /* type F */ end + 1: tmp <= rdata; + 2: {registers[`REG_PCH],registers[`REG_PCL]} <= + {registers[`REG_PCH],registers[`REG_PCL]} + + {tmp[7]?8'hFF:8'h00,tmp}; + endcase + end default: $stop; endcase