X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/a85b19a7c7e7fecb4e71c41b37fb30dabaf8bd14..9aa931d18d08b0542f8fae054fba96a9e7b095ea:/System.v

diff --git a/System.v b/System.v
index 53e6257..8fc4c9c 100644
--- a/System.v
+++ b/System.v
@@ -23,7 +23,7 @@ module InternalRAM(
 	
 	reg [7:0] ram [8191:0];
 	
-	wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+	wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
 	reg [7:0] odata;
 	wire idata = data;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
@@ -114,6 +114,13 @@ module CoreTop(
     .data(data), 
     .serial(serio)
     );
+
+  InternalRAM ram(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd));
 endmodule
 
 module TestBench();
@@ -140,21 +147,21 @@ module TestBench();
 		.wr(wr),
 		.rd(rd));
 	
-//	InternalRAM ram(
-//		.address(addr),
-//		.data(data),
-//		.clk(clk),
-//		.wr(wr),
-//		.rd(rd));
+	InternalRAM ram(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd));
 
-//	wire serio;
-//	UART uart(
-//		.addr(addr),
-//		.data(data),
-//		.clk(clk),
-//		.wr(wr),
-//		.rd(rd),
-//		.serial(serio));
+	wire serio;
+	UART uart(
+		.addr(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd),
+		.serial(serio));
 	
 //	Switches sw(
 //		.clk(clk),