X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/a02672555adf08bfd6755cf70599895dd2155a24..7d9d69c71187b4891b2281ab58ab8360e43290c2:/Uart.v

diff --git a/Uart.v b/Uart.v
index 1cc839a..f8ee27b 100644
--- a/Uart.v
+++ b/Uart.v
@@ -1,4 +1,4 @@
-`define IN_CLK 8400000
+`define IN_CLK 8388608
 `define OUT_CLK 9600
 `define CLK_DIV `IN_CLK / `OUT_CLK
 `define MMAP_ADDR 16'hFF50
@@ -21,17 +21,16 @@ module UART(
 
 	always @ (negedge clk)
 	begin
-`define FUQING 4'b1010
 		/* deal with diqing */
 		if(new) begin
-			data_stor <= ~data;
+			data_stor <= data;
 			have_data <= 1;
 			diqing <= 4'b0000;
 		end else if (clkdiv == 0) begin
 			diqing <= diqing + 1;
 			if (have_data)
 				case (diqing)
-				4'b0000: serial <= 1;
+				4'b0000: serial <= 0;
 				4'b0001: serial <= data_stor[0];
 				4'b0010: serial <= data_stor[1];
 				4'b0011: serial <= data_stor[2];
@@ -40,7 +39,7 @@ module UART(
 				4'b0110: serial <= data_stor[5];
 				4'b0111: serial <= data_stor[6];
 				4'b1000: serial <= data_stor[7];
-				4'b1001: serial <= 0;
+				4'b1001: serial <= 1;
 				4'b1010: have_data <= 0;
 				default: $stop;
 			endcase