X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/a02672555adf08bfd6755cf70599895dd2155a24..7541ec1789a729ac97d5f32e4d9360a42c759668:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index afa4495..1182b32 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -1,42 +1,89 @@
-`define REG_A 0
-`define REG_B 1
-`define REG_C 2
-`define REG_D 3
-`define REG_E 4
-`define REG_F 5
-`define REG_H 6
-`define REG_L 7
-`define REG_SPH 8
-`define REG_SPL 9
-`define REG_PCH 10
-`define REG_PCL 11
+`define REG_A	0
+`define REG_B	1
+`define REG_C	2
+`define REG_D	3
+`define REG_E	4
+`define REG_F	5
+`define REG_H	6
+`define REG_L	7
+`define REG_SPH	8
+`define REG_SPL	9
+`define REG_PCH	10
+`define REG_PCL	11
 
-`define FLAG_Z 8'b10000000
-`define FLAG_N 8'b01000000
-`define FLAG_H 8'b00100000
-`define FLAG_C 8'b00010000
+`define _A	registers[`REG_A]
+`define _B	registers[`REG_B]
+`define _C	registers[`REG_C]
+`define _D	registers[`REG_D]
+`define _E	registers[`REG_E]
+`define _F	registers[`REG_F]
+`define _H	registers[`REG_H]
+`define _L	registers[`REG_L]
+`define _SPH	registers[`REG_SPH]
+`define _SPL	registers[`REG_SPL]
+`define _PCH	registers[`REG_PCH]
+`define _PCL	registers[`REG_PCL]
+`define _AF	{`_A, `_F}
+`define _BC	{`_B, `_C}
+`define _DE	{`_D, `_E}
+`define _HL	{`_H, `_L}
+`define _SP	{`_SPH, `_SPL}
+`define _PC	{`_PCH, `_PCL}
 
-`define STATE_FETCH			2'h0
-`define STATE_DECODE			2'h1
+`define FLAG_Z	8'b10000000
+`define FLAG_N	8'b01000000
+`define FLAG_H	8'b00100000
+`define FLAG_C	8'b00010000
+
+`define STATE_FETCH		2'h0
+`define STATE_DECODE		2'h1
 `define STATE_EXECUTE		2'h2
 `define STATE_WRITEBACK		2'h3
 
-`define INSN_LD_reg_imm8	8'b00xxx110
-`define INSN_HALT				8'b01110110
-`define INSN_LD_HL_reg		8'b01110xxx
-`define INSN_LD_reg_HL		8'b01xxx110
-`define INSN_LD_reg_reg		8'b01xxxxxx
-`define INSN_LD_reg_imm16	8'b00xx0001
-`define INSN_LD_SP_HL		8'b11111001
-`define INSN_PUSH_reg		8'b11xx0101
-`define INSN_POP_reg			8'b11xx0001
-`define INSN_LDH_AC			8'b111x0010	// Either LDH A,(C) or LDH (C),A
-`define INSN_LDx_AHL			8'b001xx010	// LDD/LDI A,(HL) / (HL),A
-`define INSN_ALU8				8'b10xxxxxx	// 10 xxx yyy
-`define INSN_NOP				8'b00000000
-`define INSN_RST				8'b11xxx111
-`define INSN_RET				8'b110x1001	// 1 = RETI, 0 = RET
-`define INSN_CALL				8'b11001101
+`define INSN_LD_reg_imm8	9'b000xxx110
+`define INSN_HALT		9'b001110110
+`define INSN_LD_HL_reg		9'b001110xxx
+`define INSN_LD_reg_HL		9'b001xxx110
+`define INSN_LD_reg_reg		9'b001xxxxxx
+`define INSN_LD_reg_imm16	9'b000xx0001
+`define INSN_LD_SP_HL		9'b011111001
+`define INSN_PUSH_reg		9'b011xx0101
+`define INSN_POP_reg		9'b011xx0001
+`define INSN_LDH_AC		9'b0111x0010	// Either LDH A,(C) or LDH (C),A
+`define INSN_LDx_AHL		9'b0001xx010	// LDD/LDI A,(HL) / (HL),A
+`define INSN_ALU8		9'b010xxxxxx	// 10 xxx yyy
+`define INSN_ALU8IMM		9'b011xxx110
+`define INSN_NOP		9'b000000000
+`define INSN_RST		9'b011xxx111
+`define INSN_RET		9'b0110x1001	// 1 = RETI, 0 = RET
+`define INSN_RETCC		9'b0110xx000
+`define INSN_CALL		9'b011001101
+`define INSN_CALLCC		9'b0110xx100	// Not that call/cc.
+`define INSN_JP_imm		9'b011000011
+`define INSN_JPCC_imm		9'b0110xx010
+`define INSN_ALU_A		9'b000xxx111
+`define INSN_JP_HL		9'b011101001
+`define INSN_JR_imm		9'b000011000
+`define INSN_JRCC_imm		9'b0001xx000
+`define INSN_INCDEC16		9'b000xxx011
+`define INSN_VOP_INTR		9'b011111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
+`define INSN_DI			9'b011110011
+`define INSN_EI			9'b011111011
+`define INSN_INCDEC_HL		9'b00011010x
+`define INSN_INCDEC_reg8	9'b000xxx10x
+`define INSN_LD8M_A		9'b0111x0000	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+`define INSN_LD16M_A		9'b0111x1010	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+`define INSN_LDBCDE_A		9'b0000xx010
+`define INSN_TWO_BYTE		9'b011001011    // prefix for two-byte opqodes
+`define INSN_ALU_EXT		9'b100xxxxxx
+`define INSN_BIT		9'b101xxxxxx
+`define INSN_RES		9'b110xxxxxx
+`define INSN_SET		9'b111xxxxxx
+
+`define INSN_cc_NZ		2'b00
+`define INSN_cc_Z		2'b01
+`define INSN_cc_NC		2'b10
+`define INSN_cc_C		2'b11
 
 `define INSN_reg_A		3'b111
 `define INSN_reg_B		3'b000
@@ -45,15 +92,15 @@
 `define INSN_reg_E		3'b011
 `define INSN_reg_H		3'b100
 `define INSN_reg_L		3'b101
-`define INSN_reg_dHL	3'b110
-`define INSN_reg16_BC	2'b00
-`define INSN_reg16_DE	2'b01
-`define INSN_reg16_HL	2'b10
-`define INSN_reg16_SP	2'b11
-`define INSN_stack_AF	2'b11
-`define INSN_stack_BC	2'b00
-`define INSN_stack_DE	2'b01
-`define INSN_stack_HL	2'b10
+`define INSN_reg_dHL		3'b110
+`define INSN_reg16_BC		2'b00
+`define INSN_reg16_DE		2'b01
+`define INSN_reg16_HL		2'b10
+`define INSN_reg16_SP		2'b11
+`define INSN_stack_AF		2'b11
+`define INSN_stack_BC		2'b00
+`define INSN_stack_DE		2'b01
+`define INSN_stack_HL		2'b10
 `define INSN_alu_ADD		3'b000
 `define INSN_alu_ADC		3'b001
 `define INSN_alu_SUB		3'b010
@@ -62,68 +109,192 @@
 `define INSN_alu_XOR		3'b101
 `define INSN_alu_OR		3'b110
 `define INSN_alu_CP		3'b111		// Oh lawd, is dat some CP?
+`define INSN_alu_RLCA		3'b000
+`define INSN_alu_RRCA		3'b001
+`define INSN_alu_RLA		3'b010
+`define INSN_alu_RRA		3'b011
+`define INSN_alu_DAA		3'b100
+`define INSN_alu_CPL		3'b101
+`define INSN_alu_SCF		3'b110
+`define INSN_alu_CCF		3'b111
+`define INSN_alu_RLC		3'b000
+`define INSN_alu_RRC		3'b001
+`define INSN_alu_RL		3'b010
+`define INSN_alu_RR		3'b011
+`define INSN_alu_DA_SLA		3'b100
+`define INSN_alu_CPL_SRA	3'b101
+`define INSN_alu_SCF_SWAP	3'b110
+`define INSN_alu_CCF_SRL	3'b111
+
+`define EXEC_INC_PC 		`_PC <= `_PC + 1;
+`define EXEC_NEXTADDR_PCINC	address <= `_PC + 1;
+`define EXEC_NEWCYCLE		begin newcycle <= 1; rd <= 1; wr <= 0; end
+`define EXEC_NEWCYCLE_TWOBYTE	begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
+`ifdef verilator
+	`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end
+	`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end
+`else
+	`ifdef isim
+		`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end
+		`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end
+	`else
+/* Work around XST's retarded bugs :\ */
+		`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
+		`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end
+	`endif
+`endif
 
 module GBZ80Core(
 	input clk,
 	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] busdata,
-	output reg buswr, output reg busrd);
-	
-	reg [1:0] state = 0;					/* State within this bus cycle (see STATE_*). */
-	reg [2:0] cycle = 0;					/* Cycle for instructions. */
+	output reg buswr, output reg busrd,
+	input irq, input [7:0] jaddr,
+	output reg [1:0] state);
+
+//	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
+	reg [2:0] cycle;					/* Cycle for instructions. */
 	
 	reg [7:0] registers[11:0];
 	
 	reg [15:0] address;				/* Address for the next bus operation. */
 	
-	reg [7:0] opcode;				/* Opcode from the current machine cycle. */
-	
+	reg [8:0] opcode;				/* Opcode from the current machine cycle. */
+
 	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
-	reg rd = 1, wr = 0, newcycle = 1;
+	reg rd, wr, newcycle, twobyte;
 	
 	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
 	
 	reg [7:0] buswdata;
 	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
-	
-	reg ie = 0;
-	
+
+	reg ie, iedelay;
+
+	wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
+	wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
+	wire [7:0] alu_res;
+	wire [3:0] f_res;
+
+	assign rlc   = {tmp[6:0],tmp[7]};
+	assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
+			,2'b0,
+			tmp[7]};
+
+	assign rrc   = {tmp[0],tmp[7:1]};
+	assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
+			2'b0,
+			tmp[0]};
+
+	assign rl    = {tmp[6:0],`_F[4]};
+	assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
+			2'b0,
+			tmp[7]};
+
+	assign rr    = {`_F[4],tmp[7:1]};
+	assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
+			2'b0,
+			tmp[0]};
+
+	assign sla   = {tmp[6:0],1'b0};
+	assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
+			2'b0,
+			tmp[7]};
+
+	assign sra   = {tmp[7],tmp[7:1]};
+//	assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
+
+	assign swap  = {tmp[3:0],tmp[7:4]};
+	assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
+			3'b0};
+
+	assign srl   = {1'b0,tmp[7:1]};
+	assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
+			2'b0,
+			tmp[0]};
+	assign sraf  = srlf;
+
+	/*  Y U Q  */
+	assign {alu_res,f_res} =
+		opcode[5] ? (
+			opcode[4] ? (
+				opcode[3] ? {srl,srlf} : {swap,swapf}
+			) : (
+				opcode[3] ? {sra,sraf} : {sla,slaf}
+			)
+		) : (
+			opcode[4] ? (
+				opcode[3] ? {rr,rrf} : {rl,rlf}
+			) : (
+				opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
+			)
+		);
+
 	initial begin
-		registers[ 0] <= 0;
-		registers[ 1] <= 0;
-		registers[ 2] <= 0;
-		registers[ 3] <= 0;
-		registers[ 4] <= 0;
-		registers[ 5] <= 0;
-		registers[ 6] <= 0;
-		registers[ 7] <= 0;
-		registers[ 8] <= 0;
-		registers[ 9] <= 0;
-		registers[10] <= 0;
-		registers[11] <= 0;
+		`_A <= 0;
+		`_B <= 0;
+		`_C <= 0;
+		`_D <= 0;
+		`_E <= 0;
+		`_F <= 0;
+		`_H <= 0;
+		`_L <= 0;
+		`_PCH <= 0;
+		`_PCL <= 0;
+		`_SPH <= 0;
+		`_SPL <= 0;
+		rd <= 1;
+		wr <= 0;
+		newcycle <= 1;
+		state <= 0;
+		cycle <= 0;
+		busrd <= 0;
+		buswr <= 0;
+		busaddress <= 0;
+		ie <= 0;
+		iedelay <= 0;
+		opcode <= 0;
+		state <= `STATE_WRITEBACK;
+		cycle <= 0;
+		twobyte <= 0;
 	end
 
 	always @(posedge clk)
 		case (state)
 		`STATE_FETCH: begin
-			if (wr)
-				buswdata <= wdata;
-			if (newcycle)
-				busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
-			else
+			if (newcycle) begin
+				busaddress <= `_PC;
+				buswr <= 0;
+				busrd <= 1;
+			end else begin
 				busaddress <= address;
-			buswr <= wr;
-			busrd <= rd;
+				buswr <= wr;
+				busrd <= rd;
+				if (wr)
+					buswdata <= wdata;
+			end
 			state <= `STATE_DECODE;
 		end
 		`STATE_DECODE: begin
 			if (newcycle) begin
-				opcode <= busdata;
+				if (twobyte) begin
+					opcode <= {1'b1,busdata};
+					twobyte <= 0;
+				end else if (ie && irq)
+					opcode <= `INSN_VOP_INTR;
+				else
+					opcode <= {1'b0,busdata};
 				rdata <= busdata;
 				newcycle <= 0;
 				cycle <= 0;
-			end else
+			end else begin
 				if (rd) rdata <= busdata;
+				cycle <= cycle + 1;
+			end
+			if (iedelay) begin
+				ie <= 1;
+				iedelay <= 0;
+			end
 			buswr <= 0;
 			busrd <= 0;
 			wr <= 0;
@@ -133,285 +304,10 @@ module GBZ80Core(
 			state <= `STATE_EXECUTE;
 		end
 		`STATE_EXECUTE: begin
-`define EXEC_INC_PC \
-	{registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEXTADDR_PCINC \
-	address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEWCYCLE \
-	newcycle <= 1; rd <= 1; wr <= 0
 			casex (opcode)
-			`INSN_LD_reg_imm8: begin
-				case (cycle)
-				0:	begin
-						`EXEC_INC_PC;
-						`EXEC_NEXTADDR_PCINC;
-						rd <= 1;
-					end
-				1:	begin
-						`EXEC_INC_PC;
-						if (opcode[5:3] == `INSN_reg_dHL) begin
-							address <= {registers[`REG_H], registers[`REG_L]};
-							wdata <= rdata;
-							rd <= 0;
-							wr <= 1;
-						end else begin
-							`EXEC_NEWCYCLE;
-						end
-					end
-				2:	begin
-						`EXEC_NEWCYCLE;
-					end
-				endcase
-			end
-			`INSN_HALT: begin
-				`EXEC_NEWCYCLE;
-				/* XXX Interrupts needed for HALT. */
-			end
-			`INSN_LD_HL_reg: begin
-				case (cycle)
-				0:	begin
-						case (opcode[2:0])
-						`INSN_reg_A:	wdata <= registers[`REG_A];
-						`INSN_reg_B:	wdata <= registers[`REG_B];
-						`INSN_reg_C:	wdata <= registers[`REG_C];
-						`INSN_reg_D:	wdata <= registers[`REG_D];
-						`INSN_reg_E:	wdata <= registers[`REG_E];
-						`INSN_reg_H:	wdata <= registers[`REG_H];
-						`INSN_reg_L:	wdata <= registers[`REG_L];
-						endcase
-						address <= {registers[`REG_H], registers[`REG_L]};
-						wr <= 1; rd <= 0;
-					end
-				1:	begin
-						`EXEC_INC_PC;
-						`EXEC_NEWCYCLE;
-					end
-				endcase
-			end
-			`INSN_LD_reg_HL: begin
-				case(cycle)
-				0:	begin
-						address <= {registers[`REG_H], registers[`REG_L]};
-						rd <= 1;
-					end
-				1:	begin
-						tmp <= rdata;
-						`EXEC_INC_PC;
-						`EXEC_NEWCYCLE;
-					end
-				endcase
-			end
-			`INSN_LD_reg_reg: begin
-				`EXEC_INC_PC;
-				`EXEC_NEWCYCLE;
-				case (opcode[2:0])
-				`INSN_reg_A:	tmp <= registers[`REG_A];
-				`INSN_reg_B:	tmp <= registers[`REG_B];
-				`INSN_reg_C:	tmp <= registers[`REG_C];
-				`INSN_reg_D:	tmp <= registers[`REG_D];
-				`INSN_reg_E:	tmp <= registers[`REG_E];
-				`INSN_reg_H:	tmp <= registers[`REG_H];
-				`INSN_reg_L:	tmp <= registers[`REG_L];
-				endcase
-			end
-			`INSN_LD_reg_imm16: begin
-				`EXEC_INC_PC;
-				case (cycle)
-				0:	begin
-						`EXEC_NEXTADDR_PCINC;
-						rd <= 1;
-					end
-				1:	begin
-						`EXEC_NEXTADDR_PCINC;
-						rd <= 1;
-					end
-				2: begin `EXEC_NEWCYCLE; end
-				endcase
-			end
-			`INSN_LD_SP_HL: begin
-				case (cycle)
-				0:	begin
-						tmp <= registers[`REG_H];
-					end
-				1:	begin
-						`EXEC_NEWCYCLE;
-						`EXEC_INC_PC;
-						tmp <= registers[`REG_L];
-					end
-				endcase
-			end
-			`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
-				case (cycle)
-				0:	begin
-						wr <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
-						case (opcode[5:4])
-						`INSN_stack_AF:	wdata <= registers[`REG_A];
-						`INSN_stack_BC:	wdata <= registers[`REG_B];
-						`INSN_stack_DE:	wdata <= registers[`REG_D];
-						`INSN_stack_HL:	wdata <= registers[`REG_H];
-						endcase
-					end
-				1:	begin
-						wr <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
-						case (opcode[5:4])
-						`INSN_stack_AF:	wdata <= registers[`REG_F];
-						`INSN_stack_BC:	wdata <= registers[`REG_C];
-						`INSN_stack_DE:	wdata <= registers[`REG_E];
-						`INSN_stack_HL:	wdata <= registers[`REG_L];
-						endcase
-					end
-				2:	begin /* TWIDDLE OUR FUCKING THUMBS! */ end
-				3:	begin
-						`EXEC_NEWCYCLE;
-						`EXEC_INC_PC;
-					end
-				endcase
-			end
-			`INSN_POP_reg: begin	/* POP is 12 cycles! */
-				case (cycle)
-				0:	begin
-						rd <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]};
-					end
-				1:	begin
-						rd <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]};
-					end
-				2:	begin
-						`EXEC_NEWCYCLE;
-						`EXEC_INC_PC;
-					end
-				endcase
-			end
-			`INSN_LDH_AC: begin
-				case (cycle)
-				0:	begin
-						address <= {8'hFF,registers[`REG_C]};
-						if (opcode[4]) begin	// LD A,(C)
-							rd <= 1;
-						end else begin
-							wr <= 1;
-							wdata <= registers[`REG_A];
-						end
-					end
-				1:	begin
-						`EXEC_NEWCYCLE;
-						`EXEC_INC_PC;
-					end
-				endcase
-			end
-			`INSN_LDx_AHL: begin
-				case (cycle)
-				0:	begin
-						address <= {registers[`REG_H],registers[`REG_L]};
-						if (opcode[3]) begin	// LDx A, (HL)
-							rd <= 1;
-						end else begin
-							wr <= 1;
-							wdata <= registers[`REG_A];
-						end
-					end
-				1:	begin
-						`EXEC_NEWCYCLE;
-						`EXEC_INC_PC;
-					end
-				endcase
-			end
-			`INSN_ALU8: begin
-				if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
-					// fffffffff fuck your shit, read from (HL) :(
-					rd <= 1;
-					address <= {registers[`REG_H], registers[`REG_L]};
-				end else begin
-					`EXEC_NEWCYCLE;
-					`EXEC_INC_PC;
-					case (opcode[2:0])
-					`INSN_reg_A:	tmp <= registers[`REG_A];
-					`INSN_reg_B:	tmp <= registers[`REG_B];
-					`INSN_reg_C:	tmp <= registers[`REG_C];
-					`INSN_reg_D:	tmp <= registers[`REG_D];
-					`INSN_reg_E:	tmp <= registers[`REG_E];
-					`INSN_reg_H:	tmp <= registers[`REG_H];
-					`INSN_reg_L:	tmp <= registers[`REG_L];
-					`INSN_reg_dHL:	tmp <= rdata;
-					endcase
-				end
-			end
-			`INSN_NOP: begin
-				`EXEC_NEWCYCLE;
-				`EXEC_INC_PC;
-			end
-			`INSN_RST: begin
-				case (cycle)
-				0:	begin
-						`EXEC_INC_PC;		// This goes FIRST in RST
-					end
-				1:	begin
-						wr <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
-						wdata <= registers[`REG_PCH];
-					end
-				2:	begin
-						wr <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
-						wdata <= registers[`REG_PCL];
-					end
-				3:	begin
-						`EXEC_NEWCYCLE;
-						{registers[`REG_PCH],registers[`REG_PCL]} <=
-							{10'b0,opcode[5:3],3'b0};
-					end
-				endcase
-			end
-			`INSN_RET: begin
-				case (cycle)
-				0:	begin
-						rd <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]};
-					end
-				1:	begin
-						rd <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
-					end
-				2:	begin /* twiddle thumbs */ end
-				3:	begin
-						`EXEC_NEWCYCLE;
-						// do NOT increment PC!
-					end
-				endcase
-			end
-			`INSN_CALL: begin
-				case (cycle)
-				0:	begin
-						`EXEC_INC_PC;
-						`EXEC_NEXTADDR_PCINC;
-						rd <= 1;
-					end
-				1:	begin
-						`EXEC_INC_PC;
-						`EXEC_NEXTADDR_PCINC;
-						rd <= 1;
-					end
-				2:	begin
-						`EXEC_INC_PC;
-					end
-				3:	begin
-						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-						wdata <= registers[`REG_PCH];
-						wr <= 1;
-					end
-				4:	begin
-						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
-						wdata <= registers[`REG_PCL];
-						wr <= 1;
-					end
-				5:	begin
-						`EXEC_NEWCYCLE;	/* do NOT increment the PC */
-					end
-				endcase
-			end
+			`define EXECUTE
+			`include "allinsns.v"
+			`undef EXECUTE
 			default:
 				$stop;
 			endcase
@@ -419,282 +315,9 @@ module GBZ80Core(
 		end
 		`STATE_WRITEBACK: begin
 			casex (opcode)
-			`INSN_LD_reg_imm8:
-				case (cycle)
-				0:	cycle <= 1;
-				1:	case (opcode[5:3])
-					`INSN_reg_A:	begin registers[`REG_A] <= rdata; cycle <= 0; end
-					`INSN_reg_B:	begin registers[`REG_B] <= rdata; cycle <= 0; end
-					`INSN_reg_C:	begin registers[`REG_C] <= rdata; cycle <= 0; end
-					`INSN_reg_D:	begin registers[`REG_D] <= rdata; cycle <= 0; end
-					`INSN_reg_E:	begin registers[`REG_E] <= rdata; cycle <= 0; end
-					`INSN_reg_H:	begin registers[`REG_H] <= rdata; cycle <= 0; end
-					`INSN_reg_L:	begin registers[`REG_L] <= rdata; cycle <= 0; end
-					`INSN_reg_dHL:	cycle <= 2;
-					endcase
-				2:	cycle <= 0;
-				endcase
-			`INSN_HALT: begin
-				/* Nothing needs happen here. */
-				/* XXX Interrupts needed for HALT. */
-			end
-			`INSN_LD_HL_reg: begin
-				case (cycle)
-				0:	cycle <= 1;
-				1:	cycle <= 0;
-				endcase
-			end
-			`INSN_LD_reg_HL: begin
-				case (cycle)
-				0:	cycle <= 1;
-				1:	begin
-						case (opcode[5:3])
-						`INSN_reg_A:	registers[`REG_A] <= tmp;
-						`INSN_reg_B:	registers[`REG_B] <= tmp;
-						`INSN_reg_C:	registers[`REG_C] <= tmp;
-						`INSN_reg_D:	registers[`REG_D] <= tmp;
-						`INSN_reg_E:	registers[`REG_E] <= tmp;
-						`INSN_reg_H:	registers[`REG_H] <= tmp;
-						`INSN_reg_L:	registers[`REG_L] <= tmp;
-						endcase
-						cycle <= 0;
-					end
-				endcase
-			end
-			`INSN_LD_reg_reg: begin
-				case (opcode[5:3])
-				`INSN_reg_A:	registers[`REG_A] <= tmp;
-				`INSN_reg_B:	registers[`REG_B] <= tmp;
-				`INSN_reg_C:	registers[`REG_C] <= tmp;
-				`INSN_reg_D:	registers[`REG_D] <= tmp;
-				`INSN_reg_E:	registers[`REG_E] <= tmp;
-				`INSN_reg_H:	registers[`REG_H] <= tmp;
-				`INSN_reg_L:	registers[`REG_L] <= tmp;
-				endcase
-			end
-			`INSN_LD_reg_imm16: begin
-				case (cycle)
-				0:	cycle <= 1;
-				1:	begin
-						case (opcode[5:4])
-						`INSN_reg16_BC:	registers[`REG_C] <= rdata;
-						`INSN_reg16_DE:	registers[`REG_E] <= rdata;
-						`INSN_reg16_HL:	registers[`REG_L] <= rdata;
-						`INSN_reg16_SP:	registers[`REG_SPL] <= rdata;
-						endcase
-						cycle <= 2;
-					end
-				2: begin
-						case (opcode[5:4])
-						`INSN_reg16_BC:	registers[`REG_B] <= rdata;
-						`INSN_reg16_DE:	registers[`REG_D] <= rdata;
-						`INSN_reg16_HL:	registers[`REG_H] <= rdata;
-						`INSN_reg16_SP:	registers[`REG_SPH] <= rdata;
-						endcase
-						cycle <= 0;
-					end
-				endcase
-			end
-			`INSN_LD_SP_HL: begin
-				case (cycle)
-				0: begin
-						cycle <= 1;
-						registers[`REG_SPH] <= tmp;
-					end
-				1: begin
-						cycle <= 0;
-						registers[`REG_SPL] <= tmp;
-					end
-				endcase
-			end
-			`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
-				case (cycle)
-				0: begin
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} - 1;
-						cycle <= 1;
-					end
-				1:	begin
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} - 1;
-						cycle <= 2;
-					end
-				2:	cycle <= 3;
-				3:	cycle <= 0;
-				endcase
-			end
-			`INSN_POP_reg: begin	/* POP is 12 cycles! */
-				case (cycle)
-				0:	begin
-						cycle <= 1;
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} + 1;
-					end
-				1:	begin
-						case (opcode[5:4])
-						`INSN_stack_AF:	registers[`REG_F] <= rdata;
-						`INSN_stack_BC:	registers[`REG_C] <= rdata;
-						`INSN_stack_DE:	registers[`REG_E] <= rdata;
-						`INSN_stack_HL:	registers[`REG_L] <= rdata;
-						endcase
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} + 1;
-						cycle <= 2;
-					end
-				2:	begin
-						case (opcode[5:4])
-						`INSN_stack_AF:	registers[`REG_A] <= rdata;
-						`INSN_stack_BC:	registers[`REG_B] <= rdata;
-						`INSN_stack_DE:	registers[`REG_D] <= rdata;
-						`INSN_stack_HL:	registers[`REG_H] <= rdata;
-						endcase
-						cycle <= 0;
-					end
-				endcase
-			end
-			`INSN_LDH_AC: begin
-				case (cycle)
-				0:	cycle <= 1;
-				1: begin
-						cycle <= 0;
-						if (opcode[4])
-							registers[`REG_A] <= rdata;
-					end
-				endcase
-			end
-			`INSN_LDx_AHL: begin
-				case (cycle)
-				0:	cycle <= 1;
-				1:	begin
-						cycle <= 0;
-						if (opcode[3])
-							registers[`REG_A] <= rdata;
-						{registers[`REG_H],registers[`REG_L]} <=
-							opcode[4] ? // if set, LDD, else LDI
-							({registers[`REG_H],registers[`REG_L]} - 1) :
-							({registers[`REG_H],registers[`REG_L]} + 1);
-					end
-				endcase
-			end
-			`INSN_ALU8: begin
-				if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
-					/* Sit on our asses. */
-					cycle <= 1;
-				end else begin		/* Actually do the computation! */
-					case (opcode[5:3])
-					`INSN_alu_ADD: begin
-						registers[`REG_A] <=
-							registers[`REG_A] + tmp;
-						registers[`REG_F] <=
-							{ /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
-							  /* N */ 1'b0,
-							  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-							  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-							  registers[`REG_F][3:0]
-							};
-					end
-					`INSN_alu_ADC: begin
-						registers[`REG_A] <=
-							registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
-						registers[`REG_F] <=
-							{ /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
-							  /* N */ 1'b0,
-							  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
-							  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
-							  registers[`REG_F][3:0]
-							};
-					end
-					`INSN_alu_AND: begin
-						registers[`REG_A] <=
-							registers[`REG_A] & tmp;
-						registers[`REG_F] <=
-							{ /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
-							  3'b010,
-							  registers[`REG_F][3:0]
-							};
-					end
-					`INSN_alu_OR: begin
-						registers[`REG_A] <=
-							registers[`REG_A] | tmp;
-						registers[`REG_F] <=
-							{ /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
-							  3'b000,
-							  registers[`REG_F][3:0]
-							};
-					end
-					`INSN_alu_XOR: begin
-						registers[`REG_A] <=
-							registers[`REG_A] ^ tmp;
-						registers[`REG_F] <=
-							{ /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
-							  3'b000,
-							  registers[`REG_F][3:0]
-							};
-					end
-					default:
-						$stop;
-					endcase
-				end
-			end
-			`INSN_NOP: begin /* NOP! */ end
-			`INSN_RST: begin
-				case (cycle)
-				0:	cycle <= 1;
-				1:	cycle <= 2;
-				2:	cycle <= 3;
-				3:	begin
-						cycle <= 0;
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]}-2;
-					end
-				endcase
-			end
-			`INSN_RET: begin
-				case (cycle)
-				0:	cycle <= 1;
-				1:	begin
-						cycle <= 2;
-						registers[`REG_PCL] <= rdata;
-					end
-				2:	begin
-						cycle <= 3;
-						registers[`REG_PCH] <= rdata;
-					end
-				3:	begin
-						cycle <= 0;
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} + 2;
-						if (opcode[4])	/* RETI */
-							ie <= 1;
-					end
-				endcase
-			end
-			`INSN_CALL: begin
-				case (cycle)
-				0:	cycle <= 1;
-				1:	begin
-						cycle <= 2;
-						tmp <= rdata;	// tmp contains newpcl
-					end
-				2:	begin
-						cycle <= 3;
-						tmp2 <= rdata;	// tmp2 contains newpch
-					end
-				3: begin
-						cycle <= 4;
-					end
-				4: begin
-						cycle <= 5;
-						registers[`REG_PCH] <= tmp2;
-					end
-				5: begin
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} - 2;
-						registers[`REG_PCL] <= tmp;
-						cycle <= 0;
-					end
-				endcase
-			end
+			`define WRITEBACK
+			`include "allinsns.v"
+			`undef WRITEBACK
 			default:
 				$stop;
 			endcase
@@ -702,146 +325,3 @@ module GBZ80Core(
 		end
 		endcase
 endmodule
-
-`timescale 1ns / 1ps
-module ROM(
-	input [15:0] address,
-	inout [7:0] data,
-	input clk,
-	input wr, rd);
-
-	reg [7:0] rom [2047:0];
-	initial $readmemh("rom.hex", rom);
-
-	wire decode = address[15:13] == 0;
-	wire [7:0] odata = rom[address[11:0]];
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-	//assign data = rd ? odata : 8'bzzzzzzzz;
-endmodule
-
-module InternalRAM(
-	input [15:0] address,
-	inout [7:0] data,
-	input clk,
-	input wr, rd);
-	
-	reg [7:0] ram [8191:0];
-	
-	wire decode = (address >= 16'hC000) && (address < 16'hFE00);
-	reg [7:0] odata;
-	wire idata = data;
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-	
-	always @(negedge clk)
-	begin
-		if (decode && rd)
-			odata <= ram[address[12:0]];
-		else if (decode && wr)
-			ram[address[12:0]] <= data;
-	end
-endmodule
-
-//module Switches(
-//	input [15:0] address,
-//	inout [7:0] data,
-//	input clk,
-//	input wr, rd,
-//	input [7:0] switches,
-//	output reg [7:0] ledout);
-	
-//	wire decode = address == 16'hFF51;
-//	reg [7:0] odata;
-//	wire idata = data;
-//	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-	
-//	always @(negedge clk)
-//	begin
-//		if (decode && rd)
-//			odata <= switches;
-//		else if (decode && wr)
-//			ledout <= data;
-//	end
-//endmodule
-
-module CoreTop(
-	input iclk,
-	output wire [7:0] leds,
-	output serio);
-	
-	wire clk;
-	IBUFG ibuf (.O(clk), .I(iclk));
-
-	wire [15:0] addr;
-	wire [7:0] data;
-	wire wr, rd;
-	
-	wire [7:0] swleds;
-	
-	assign leds = clk?{rd,wr,addr[5:0]}:data[7:0];
-
-	GBZ80Core core(
-		.clk(clk),
-		.busaddress(addr),
-		.busdata(data),
-		.buswr(wr),
-		.busrd(rd));
-	
-	ROM rom(
-		.address(addr),
-		.data(data),
-		.clk(clk),
-		.wr(wr),
-		.rd(rd));
-	
-	assign serio = 0;
-endmodule
-
-//module TestBench();
-//	reg clk = 0;
-//	wire [15:0] addr;
-//	wire [7:0] data;
-//	wire wr, rd;
-	
-//	wire [7:0] leds;
-//	wire [7:0] switches;
-	
-//	always #10 clk <= ~clk;
-//	GBZ80Core core(
-//		.clk(clk),
-//		.busaddress(addr),
-//		.busdata(data),
-//		.buswr(wr),
-//		.busrd(rd));
-	
-//	ROM rom(
-//		.clk(clk),
-//		.address(addr),
-//		.data(data),
-//		.wr(wr),
-//		.rd(rd));
-	
-//	InternalRAM ram(
-//		.address(addr),
-//		.data(data),
-//		.clk(clk),
-//		.wr(wr),
-//		.rd(rd));
-
-//	wire serio;
-//	UART uart(
-//		.addr(addr),
-//		.data(data),
-//		.clk(clk),
-//		.wr(wr),
-//		.rd(rd),
-//		.serial(serio));
-	
-//	Switches sw(
-//		.clk(clk),
-//		.address(addr),
-//		.data(data),
-//		.wr(wr),
-//		.rd(rd),
-//		.switches(switches),
-//		.leds(leds));
-//endmodule