X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/9c834ff2149ba2b9b4db71a1bb6b974235c88273..refs/heads/master:/7seg.v

diff --git a/7seg.v b/7seg.v
index c64e7d5..11e26d4 100644
--- a/7seg.v
+++ b/7seg.v
@@ -1,8 +1,9 @@
 module AddrMon(
 	input [15:0] addr,
 	input clk,
+	input [3:0] periods,
 	output reg [3:0] digit,
-	output reg [7:0] out,
+	output wire [7:0] out,
 	input freeze
 	);
 
@@ -15,9 +16,16 @@ module AddrMon(
 		(dcount == 2'b00) ? latch[3:0]  :
 		(dcount == 2'b01) ? latch[7:4]  :
 		(dcount == 2'b10) ? latch[11:8] :
-		                     latch[15:12];
+		                    latch[15:12];
+	
+	reg [6:0] odigit;
+	assign out = {odigit,
+			~((dcount == 2'b00) ? periods[0] :
+			  (dcount == 2'b01) ? periods[1] :
+			  (dcount == 2'b10) ? periods[2] :
+			                      periods[3]) };
 
-	always @ (negedge clk) begin
+	always @ (posedge clk) begin
 		if (clkdv == 31) begin
 			clkdv <= 0;
 			dcount <= dcount + 1;
@@ -31,25 +39,26 @@ module AddrMon(
 
 			case(curval)
 							/* ABCDEFGP */
-			4'h0: out <= ~8'b11111100;
-			4'h1: out <= ~8'b01100000;
-			4'h2: out <= ~8'b11011010;
-			4'h3: out <= ~8'b11110010;
-			4'h4: out <= ~8'b01100110;
-			4'h5: out <= ~8'b10110110;
-			4'h6: out <= ~8'b10111110;
-			4'h7: out <= ~8'b11100000;
-			4'h8: out <= ~8'b11111110;
-			4'h9: out <= ~8'b11110110;
-			4'hA: out <= ~8'b11101110;
-			4'hB: out <= ~8'b00111110;
-			4'hC: out <= ~8'b10011100;
-			4'hD: out <= ~8'b01111010;
-			4'hE: out <= ~8'b10011110;
-			4'hF: out <= ~8'b10001110;
+			4'h0: odigit <= ~8'b1111110;
+			4'h1: odigit <= ~8'b0110000;
+			4'h2: odigit <= ~8'b1101101;
+			4'h3: odigit <= ~8'b1111001;
+			4'h4: odigit <= ~8'b0110011;
+			4'h5: odigit <= ~8'b1011011;
+			4'h6: odigit <= ~8'b1011111;
+			4'h7: odigit <= ~8'b1110000;
+			4'h8: odigit <= ~8'b1111111;
+			4'h9: odigit <= ~8'b1111011;
+			4'hA: odigit <= ~8'b1110111;
+			4'hB: odigit <= ~8'b0011111;
+			4'hC: odigit <= ~8'b1001110;
+			4'hD: odigit <= ~8'b0111101;
+			4'hE: odigit <= ~8'b1001111;
+			4'hF: odigit <= ~8'b1000111;
 			endcase
 		end else
 			clkdv <= clkdv + 1;
+		
 		if (~freeze)
 			latch <= addr;
 	end