X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/9c834ff2149ba2b9b4db71a1bb6b974235c88273..f888201b9894683abfff012bd68b641319fb2744:/Makefile

diff --git a/Makefile b/Makefile
index d89b586..26e2289 100644
--- a/Makefile
+++ b/Makefile
@@ -1,12 +1,19 @@
-VLOGS=Uart.v Timer.v Interrupt.v GBZ80Core.v CPUDCM.v 7seg.v System.v
+VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
+	insn_jr-jrcc.v insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v \
+	insn_ret-retcc.v Interrupt.v Uart.v allinsns.v insn_alu8.v \
+	insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v insn_ld_reg_imm16.v \
+	insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \
+	insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
+	insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
+	Timer.v
 
-all: CoreTop.svf CoreTop.twr
+all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr
 
-CoreTyp.ngc: CoreTop.xst CoreTop.prj $(VLOGS) CoreTop.ucf
+CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS)
 	xst -ifn CoreTop.xst -ofn CoreTop.syr
 
-CoreTop.ngd: CoreTop.ngc foo.bmm
-	ngdbuild -dd _ngo  -nt timestamp -i -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
+CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
+	ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
 
 CoreTop_map.ncd: CoreTop.ngd
 	map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
@@ -20,17 +27,39 @@ CoreTop.twr: CoreTop_map.ncd
 CoreTop.bit: CoreTop.ut CoreTop.ncd
 	bitgen -f CoreTop.ut CoreTop.ncd
 
-CoreTop_rom.bit: rom.hex CoreTop.bit foo_bd.bmm
-	data2mem -bm foo_bd.bmm -bd rom.mem -bt CoreTop.bit -o b CoreTop_rom.bit
+netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
+	netgen -ise FPGABoy.ise -s 5  -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
 
-CoreTop.svf: CoreTop_rom.bit rom.hex impact.cmd
-	impact -batch impact.cmd
+netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
+	vlogcomp netgen/par/CoreTop_timesim.v
+	vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
+	
+CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
+	fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
 
-rom.o: rom.asm
-	rgbasm -orom.o rom.asm
+parsim: CoreTop_isim_par.exe
 
-rom.bin: rom.o rom.lnk
-	xlink rom.lnk
+%.o: %.asm
+	rgbasm -o$@ $<
 
-rom.hex: rom.bin
-	./mashrom < rom.bin > rom.hex
+%.bin: %.o rom.lnk
+	echo "[Objects]" > tmp.lnk
+	echo $< >> tmp.lnk
+	echo "" >> tmp.lnk
+	echo "[Output]" >> tmp.lnk
+	echo $@ >> tmp.lnk
+	xlink tmp.lnk
+	rm tmp.lnk
+
+%.mem: %.bin
+	./mashrom < $< > $@
+
+CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
+	data2mem -bm foo_bd.bmm -bd $< -bt CoreTop.bit -o b $@
+
+CoreTop_%.svf: CoreTop_%.bit impact.cmd
+	sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
+	impact -batch tmp.cmd
+
+parsim: CoreTop
+	
\ No newline at end of file