X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/9aa931d18d08b0542f8fae054fba96a9e7b095ea..dadf7990cbca24581bbb3c036df717dd59bdea41:/System.v diff --git a/System.v b/System.v index 8fc4c9c..8bc14e9 100644 --- a/System.v +++ b/System.v @@ -21,19 +21,22 @@ module InternalRAM( input clk, input wr, rd); + // synthesis attribute ram_style of reg is block reg [7:0] ram [8191:0]; - wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00); + wire decode = address[15:13] == 3'b110; reg [7:0] odata; wire idata = data; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; always @(negedge clk) begin - if (decode && rd) + if (decode) // This has to go this way. The only way XST knows how to do + begin // block ram is chip select, write enable, and always + if (wr) // reading. "else if rd" does not cut it ... + ram[address[12:0]] <= data; odata <= ram[address[12:0]]; - else if (decode && wr) - ram[address[12:0]] <= data; + end end endmodule @@ -61,6 +64,7 @@ endmodule module CoreTop( input xtal, input [7:0] switches, + input [3:0] buttons, output wire [7:0] leds, output serio, output wire [3:0] digits, @@ -93,7 +97,8 @@ module CoreTop( .addr(addr), .clk(clk), .digit(digits), - .out(seven) + .out(seven), + .freeze(buttons[0]) ); Switches sw(