X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/9aa931d18d08b0542f8fae054fba96a9e7b095ea..537e1f833b8eba858c06053ea6006ea608b9a5cc:/System.v diff --git a/System.v b/System.v index 8fc4c9c..712dd75 100644 --- a/System.v +++ b/System.v @@ -21,19 +21,21 @@ module InternalRAM( input clk, input wr, rd); + // synthesis attribute ram_style of reg is block reg [7:0] ram [8191:0]; - wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00); + wire decode = address[15:13] == 3'b110; reg [7:0] odata; - wire idata = data; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; always @(negedge clk) begin - if (decode && rd) + if (decode) // This has to go this way. The only way XST knows how to do + begin // block ram is chip select, write enable, and always + if (wr) // reading. "else if rd" does not cut it ... + ram[address[12:0]] <= data; odata <= ram[address[12:0]]; - else if (decode && wr) - ram[address[12:0]] <= data; + end end endmodule @@ -43,7 +45,7 @@ module Switches( input clk, input wr, rd, input [7:0] switches, - output reg [7:0] ledout); + output reg [7:0] ledout = 0); wire decode = address == 16'hFF51; reg [7:0] odata; @@ -61,26 +63,32 @@ endmodule module CoreTop( input xtal, input [7:0] switches, + input [3:0] buttons, output wire [7:0] leds, output serio, output wire [3:0] digits, output wire [7:0] seven); - wire clk; - //IBUFG ibuf (.O(clk), .I(iclk)); - + wire clk; CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk)); - + wire [15:0] addr; wire [7:0] data; wire wr, rd; - + + wire irq, tmrirq, lcdcirq; + wire [7:0] jaddr; + wire [1:0] state; + GBZ80Core core( .clk(clk), .busaddress(addr), .busdata(data), .buswr(wr), - .busrd(rd)); + .busrd(rd), + .irq(irq), + .jaddr(jaddr), + .state(state)); ROM rom( .address(addr), @@ -89,12 +97,25 @@ module CoreTop( .wr(wr), .rd(rd)); + LCDC lcdc( + .addr(addr), + .data(data), + .clk(clk), + .wr(wr), + .rd(rd), + .irq(lcdcirq)); + AddrMon amon( - .addr(addr), - .clk(clk), - .digit(digits), - .out(seven) - ); + .addr(addr), + .clk(clk), + .digit(digits), + .out(seven), + .freeze(buttons[0]), + .periods( + (state == 2'b00) ? 4'b0010 : + (state == 2'b01) ? 4'b0001 : + (state == 2'b10) ? 4'b1000 : + 4'b0100) ); Switches sw( .address(addr), @@ -106,39 +127,68 @@ module CoreTop( .switches(switches) ); - UART nouart ( - .clk(clk), - .wr(wr), - .rd(rd), - .addr(addr), - .data(data), - .serial(serio) - ); + UART nouart ( /* no u */ + .clk(clk), + .wr(wr), + .rd(rd), + .addr(addr), + .data(data), + .serial(serio) + ); - InternalRAM ram( + InternalRAM ram( .address(addr), .data(data), .clk(clk), .wr(wr), - .rd(rd)); + .rd(rd) + ); + + Timer tmr( + .clk(clk), + .wr(wr), + .rd(rd), + .addr(addr), + .data(data), + .irq(tmrirq) + ); + + Interrupt intr( + .clk(clk), + .rd(rd), + .wr(wr), + .addr(addr), + .data(data), + .vblank(0), + .lcdc(lcdcirq), + .tovf(tmrirq), + .serial(0), + .buttons(0), + .master(irq), + .jaddr(jaddr)); endmodule module TestBench(); - reg clk = 0; + reg clk = 1; wire [15:0] addr; wire [7:0] data; wire wr, rd; -// wire [7:0] leds; -// wire [7:0] switches; + wire irq, tmrirq; + wire [7:0] jaddr; + + wire [7:0] leds; + wire [7:0] switches; - always #10 clk <= ~clk; + always #62 clk <= ~clk; GBZ80Core core( .clk(clk), .busaddress(addr), .busdata(data), .buswr(wr), - .busrd(rd)); + .busrd(rd), + .irq(irq), + .jaddr(jaddr)); ROM rom( .clk(clk), @@ -163,12 +213,34 @@ module TestBench(); .rd(rd), .serial(serio)); -// Switches sw( -// .clk(clk), -// .address(addr), -// .data(data), -// .wr(wr), -// .rd(rd), -// .switches(switches), -// .leds(leds)); + Timer tmr( + .clk(clk), + .wr(wr), + .rd(rd), + .addr(addr), + .data(data), + .irq(tmrirq)); + + Interrupt intr( + .clk(clk), + .rd(rd), + .wr(wr), + .addr(addr), + .data(data), + .vblank(0), + .lcdc(0), + .tovf(tmrirq), + .serial(0), + .buttons(0), + .master(irq), + .jaddr(jaddr)); + + Switches sw( + .clk(clk), + .address(addr), + .data(data), + .wr(wr), + .rd(rd), + .switches(switches), + .ledout(leds)); endmodule