X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/91c74a3f7409b5ac9bdbd46fbff13c513b19bc9c..d1b404569fd0bdc74a3397c4ef0a5c2e5f95c835:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index ec882da..29aab52 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -152,7 +152,7 @@ module GBZ80Core(
 	inout [15:0] bus1address,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] bus1data,
 	inout bus1wr, bus1rd,
-	input irq, input [7:0] jaddr,
+	input irq, output reg irqack, input [7:0] jaddr,
 	output reg [1:0] state);
 
 //	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
@@ -177,17 +177,21 @@ module GBZ80Core(
 	
 	reg bootstrap_enb;
 	
-	wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF));	/* 0 or 1 depending on which bus */
+	wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF))	/* 0 or 1 depending on which bus */
+		`ifdef isim
+			|| (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
+		`endif
+			;
 		
 	assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
 	assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
 	assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
 	assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
 	assign busdata = (bus == 0) ? bus0data : bus1data;
-	assign bus0rd = (bus == 0) ? busrd : 1'bz;
-	assign bus1rd = (bus == 1) ? busrd : 1'bz;
-	assign bus0wr = (bus == 0) ? buswr : 1'bz;
-	assign bus1wr = (bus == 1) ? buswr : 1'bz;
+	assign bus0rd = (bus == 0) ? busrd : 1'b0;
+	assign bus1rd = (bus == 1) ? busrd : 1'b0;
+	assign bus0wr = (bus == 0) ? buswr : 1'b0;
+	assign bus1wr = (bus == 1) ? buswr : 1'b0;
 
 	reg ie, iedelay;
 
@@ -278,9 +282,10 @@ module GBZ80Core(
 		cycle <= 0;
 		twobyte <= 0;
 		bootstrap_enb <= 1;
+		irqack <= 0;
 	end
 
-	always @(posedge clk)
+	always @(negedge clk)	/* Set things up at the negedge to prepare for the posedge. */
 		case (state)
 		`STATE_FETCH: begin
 			if (newcycle) begin
@@ -291,9 +296,23 @@ module GBZ80Core(
 				busaddress <= address;
 				buswr <= wr;
 				busrd <= rd;
-				if (wr)
+				if (wr) begin
 					buswdata <= wdata;
+					if (address == 16'hFF50)
+						bootstrap_enb <= 0;
+				end
 			end
+		end
+		`STATE_DECODE: begin	/* Make sure this only happens for one clock. */
+			buswr <= 0;
+			busrd <= 0;
+		end
+		endcase
+	
+	always @(posedge clk)
+		case (state)
+		`STATE_FETCH: begin
+			/* Things are set up in negedge so that something looking on posedge will get his shit. */
 			state <= `STATE_DECODE;
 		end
 		`STATE_DECODE: begin
@@ -305,19 +324,17 @@ module GBZ80Core(
 					opcode <= `INSN_VOP_INTR;
 				else
 					opcode <= {1'b0,busdata};
-				rdata <= busdata;
 				newcycle <= 0;
+				rdata <= busdata;
 				cycle <= 0;
 			end else begin
-				if (rd) rdata <= busdata;
+				if (rd) rdata <= busdata;	/* Still valid because peripherals are now expected to keep it held valid. */
 				cycle <= cycle + 1;
 			end
 			if (iedelay) begin
 				ie <= 1;
 				iedelay <= 0;
 			end
-			buswr <= 0;
-			busrd <= 0;
 			wr <= 0;
 			rd <= 0;
 			address <= 16'bxxxxxxxxxxxxxxxx;	// Make it obvious if something of type has happened.
@@ -325,6 +342,10 @@ module GBZ80Core(
 			state <= `STATE_EXECUTE;
 		end
 		`STATE_EXECUTE: begin
+		`ifdef isim
+			if (opcode[7:0] === 8'bxxxxxxxx)
+				$stop;
+		`endif
 			casex (opcode)
 			`define EXECUTE
 			`include "allinsns.v"