X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/91c74a3f7409b5ac9bdbd46fbff13c513b19bc9c..2854e3991ab66f6fb954aba96caf7875d049431e:/System.v?ds=inline

diff --git a/System.v b/System.v
index 4c5f85b..1872e51 100644
--- a/System.v
+++ b/System.v
@@ -6,12 +6,15 @@ module ROM(
 	input clk,
 	input wr, rd);
 
+	reg [7:0] odata;
+
 	// synthesis attribute ram_style of rom is block
 	reg [7:0] rom [1023:0];
 	initial $readmemh("rom.hex", rom);
 
 	wire decode = address[15:13] == 0;
-	wire [7:0] odata = rom[address[10:0]];
+	always @(posedge clk)
+		odata <= rom[address[10:0]];
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 endmodule
 
@@ -21,11 +24,11 @@ module BootstrapROM(
 	input clk,
 	input wr, rd);
 
-	reg [7:0] rom [255:0];
-	initial $readmemh("bootstrap.hex", rom);
+	reg [7:0] brom [255:0];
+	initial $readmemh("bootstrap.hex", brom);
 
 	wire decode = address[15:8] == 0;
-	wire [7:0] odata = rom[address[7:0]];
+	wire [7:0] odata = brom[address[7:0]];
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 endmodule
 
@@ -41,7 +44,7 @@ module MiniRAM(
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode)	// This has to go this way. The only way XST knows how to do
 		begin				// block ram is chip select, write enable, and always
@@ -65,7 +68,7 @@ module InternalRAM(
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode)	// This has to go this way. The only way XST knows how to do
 		begin				// block ram is chip select, write enable, and always
@@ -88,7 +91,7 @@ module Switches(
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode && rd)
 			odata <= switches;