X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/91c74a3f7409b5ac9bdbd46fbff13c513b19bc9c..2854e3991ab66f6fb954aba96caf7875d049431e:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index ec882da..9db958f 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -280,7 +280,7 @@ module GBZ80Core(
 		bootstrap_enb <= 1;
 	end
 
-	always @(posedge clk)
+	always @(negedge clk)	/* Set things up at the negedge to prepare for the posedge. */
 		case (state)
 		`STATE_FETCH: begin
 			if (newcycle) begin
@@ -294,6 +294,15 @@ module GBZ80Core(
 				if (wr)
 					buswdata <= wdata;
 			end
+		end
+		`STATE_DECODE: begin	/* Make sure this only happens for one clock. */
+		end
+		endcase
+	
+	always @(posedge clk)
+		case (state)
+		`STATE_FETCH: begin
+			/* Things are set up in negedge so that something looking on posedge will get his shit. */
 			state <= `STATE_DECODE;
 		end
 		`STATE_DECODE: begin
@@ -305,8 +314,8 @@ module GBZ80Core(
 					opcode <= `INSN_VOP_INTR;
 				else
 					opcode <= {1'b0,busdata};
-				rdata <= busdata;
 				newcycle <= 0;
+				rdata <= busdata;
 				cycle <= 0;
 			end else begin
 				if (rd) rdata <= busdata;
@@ -316,10 +325,10 @@ module GBZ80Core(
 				ie <= 1;
 				iedelay <= 0;
 			end
-			buswr <= 0;
-			busrd <= 0;
 			wr <= 0;
 			rd <= 0;
+			buswr <= 0;
+			busrd <= 0;
 			address <= 16'bxxxxxxxxxxxxxxxx;	// Make it obvious if something of type has happened.
 			wdata <= 8'bxxxxxxxx;
 			state <= `STATE_EXECUTE;