X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/7d9d69c71187b4891b2281ab58ab8360e43290c2..fc443a4f61b38236a17ab2928bd90327edc68266:/Uart.v diff --git a/Uart.v b/Uart.v index f8ee27b..3dd1532 100644 --- a/Uart.v +++ b/Uart.v @@ -8,16 +8,22 @@ module UART( input wr, input rd, input [15:0] addr, - input [7:0] data, - output reg serial); + inout [7:0] data, + output reg serial = 1); + + wire decode = (addr == `MMAP_ADDR); + + wire [7:0] odata; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; reg [7:0] data_stor = 0; reg [15:0] clkdiv = 0; reg have_data = 0; - reg data_end = 0; reg [3:0] diqing = 4'b0000; - wire new = (wr) && (!have_data) && (addr == `MMAP_ADDR); + wire new = (wr) && (!have_data) && decode; + + assign odata = have_data ? 8'b1 : 8'b0; always @ (negedge clk) begin