X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/7d9d69c71187b4891b2281ab58ab8360e43290c2..75ab1e9975f64989ee18450eb09b66b33ec5def8:/Uart.v diff --git a/Uart.v b/Uart.v index f8ee27b..af173ca 100644 --- a/Uart.v +++ b/Uart.v @@ -1,5 +1,5 @@ `define IN_CLK 8388608 -`define OUT_CLK 9600 +`define OUT_CLK 57600 `define CLK_DIV `IN_CLK / `OUT_CLK `define MMAP_ADDR 16'hFF50 @@ -8,16 +8,22 @@ module UART( input wr, input rd, input [15:0] addr, - input [7:0] data, - output reg serial); + inout [7:0] data, + output reg serial = 1); + + wire decode = (addr == `MMAP_ADDR); + + wire [7:0] odata; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; reg [7:0] data_stor = 0; reg [15:0] clkdiv = 0; reg have_data = 0; - reg data_end = 0; reg [3:0] diqing = 4'b0000; - wire new = (wr) && (!have_data) && (addr == `MMAP_ADDR); + wire new = (wr) && (!have_data) && decode; + + assign odata = have_data ? 8'b1 : 8'b0; always @ (negedge clk) begin