X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/74610a872e3bead82589e6ea786e928f319540e4..a8f4468d0cd6910eba8031e21038d76857a2c107:/LCDC.v

diff --git a/LCDC.v b/LCDC.v
index a198c45..add6893 100644
--- a/LCDC.v
+++ b/LCDC.v
@@ -21,6 +21,10 @@ module LCDC(
 	output wire lcdclk, lcdvs, lcdhs,
 	output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb);
 	
+	/***** Bus latches *****/
+	reg rdlatch = 0;
+	reg [15:0] addrlatch = 0;
+	
 	/***** Needed prototypes *****/
 	wire [1:0] pixdata;
 	
@@ -172,26 +176,28 @@ module LCDC(
 	end
   
 	/***** Bus interface *****/
-	assign data = rd ?
-			((addr == `ADDR_LCDC) ? rLCDC :
-			 (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
-			 (addr == `ADDR_SCY) ? rSCY :
-			 (addr == `ADDR_SCX) ? rSCX :
-			 (addr == `ADDR_LY) ? posy :
-			 (addr == `ADDR_LYC) ? rLYC :
-			 (addr == `ADDR_BGP) ? rBGP :
-			 (addr == `ADDR_OBP0) ? rOBP0 :
-			 (addr == `ADDR_OBP1) ? rOBP1 :
-			 (addr == `ADDR_WY) ? rWY :
-			 (addr == `ADDR_WX) ? rWX :
-			 (decode_tiledata && addr[0]) ? tilehigh :
-			 (decode_tiledata && ~addr[0]) ? tilelow :
+	assign data = rdlatch ?
+			((addrlatch == `ADDR_LCDC) ? rLCDC :
+			 (addrlatch == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
+			 (addrlatch == `ADDR_SCY) ? rSCY :
+			 (addrlatch == `ADDR_SCX) ? rSCX :
+			 (addrlatch == `ADDR_LY) ? posy :
+			 (addrlatch == `ADDR_LYC) ? rLYC :
+			 (addrlatch == `ADDR_BGP) ? rBGP :
+			 (addrlatch == `ADDR_OBP0) ? rOBP0 :
+			 (addrlatch == `ADDR_OBP1) ? rOBP1 :
+			 (addrlatch == `ADDR_WY) ? rWY :
+			 (addrlatch == `ADDR_WX) ? rWX :
+			 (decode_tiledata && addrlatch[0]) ? tilehigh :
+			 (decode_tiledata && ~addrlatch[0]) ? tilelow :
 			 (decode_bgmap1) ? tileno :
 			 8'bzzzzzzzz) :
 		8'bzzzzzzzz;
   
 	always @(posedge clk)
 	begin
+		rdlatch <= rd;
+		addrlatch <= addr;
 		if (wr)
 			case (addr)
 			`ADDR_LCDC:	rLCDC <= data;