X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/722e486a9ea69af1fdad7d0d31490bb2845881ec..f26748f71f3f39de15a1c07f95c15f8c4481f452:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 77c3649..3cd46e3 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -36,6 +36,7 @@
 `define INSN_NOP				8'b00000000
 `define INSN_RST				8'b11xxx111
 `define INSN_RET				8'b110x1001	// 1 = RETI, 0 = RET
+`define INSN_RETCC			8'b110xx000
 `define INSN_CALL				8'b11001101
 `define INSN_CALLCC			8'b110xx100	// Not that call/cc.
 `define INSN_JP_imm			8'b11000011
@@ -400,18 +401,29 @@ module GBZ80Core(
 					end
 				endcase
 			end
-			`INSN_RET: begin
+			`INSN_RET,`INSN_RETCC: begin
 				case (cycle)
 				0:	begin
 						rd <= 1;
 						address <= {registers[`REG_SPH],registers[`REG_SPL]};
 					end
-				1:	begin
+				1:	begin	// SPECIAL CASE: cycle does NOT increase linearly with ret!
+						`EXEC_INC_PC;
+						case (opcode[4:3])	// cycle 1 is skipped if we are not retcc
+						`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+						`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+						`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+						`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+						endcase
+						rd <= 1;
+						address <= {registers[`REG_SPH],registers[`REG_SPL]};
+					end
+				2:	begin
 						rd <= 1;
 						address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
 					end
-				2:	begin /* twiddle thumbs */ end
-				3:	begin
+				3:	begin /* twiddle thumbs */ end
+				4:	begin
 						`EXEC_NEWCYCLE;
 						// do NOT increment PC!
 					end
@@ -778,15 +790,17 @@ module GBZ80Core(
 						{registers[`REG_SPH],registers[`REG_SPL]}-2;
 				endcase
 			end
-			`INSN_RET: begin
+			`INSN_RET,`INSN_RETCC: begin
 				case (cycle)
-				0:	begin /* type F */ end
-				1:	registers[`REG_PCL] <= rdata;
-				2:	registers[`REG_PCH] <= rdata;
-				3:	begin
+				0:	if (opcode[0])	// i.e., not RETCC
+						cycle <= 1;	// Skip cycle 1; it gets incremented on the next round.
+				1: begin /* Nothing need happen here. */ end
+				2:	registers[`REG_PCL] <= rdata;
+				3:	registers[`REG_PCH] <= rdata;
+				4:	begin
 						{registers[`REG_SPH],registers[`REG_SPL]} <=
 							{registers[`REG_SPH],registers[`REG_SPL]} + 2;
-						if (opcode[4])	/* RETI */
+						if (opcode[4] && (opcode != `INSN_RETCC))	/* RETI */
 							ie <= 1;
 					end
 				endcase