X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/722e486a9ea69af1fdad7d0d31490bb2845881ec..06ad3a30038ac8ca45dd7b0c34213c0c8335c17c:/rom.asm

diff --git a/rom.asm b/rom.asm
index c2b7598..93f8524 100644
--- a/rom.asm
+++ b/rom.asm
@@ -16,7 +16,7 @@ main:
 
 	call waitsw
 
-	jp main
+	jr main
 
 signon:
 	db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
@@ -33,10 +33,10 @@ memtest:
 	ld [hli],a
 	ld a, $DF
 	cp h
-	jp nz, .wr
+	jr nz, .wr
 	ld a, $80
 	cp l
-	jp nz, .wr
+	jr nz, .wr
 
 	ld hl, $C000		; Read loop
 .rd:
@@ -45,14 +45,14 @@ memtest:
 	ld b,a
 	ld a, [hli]
 	cp b
-	jp nz, .memfail
+	jr nz, .memfail
 	
 	ld a, $DF
 	cp h
-	jp nz, .rd
+	jr nz, .rd
 	ld a, $80
 	cp l
-	jp nz, .rd
+	jr nz, .rd
 	
 	ld hl, testokstr	; Say we're OK
 	call puts
@@ -104,24 +104,48 @@ waitsw:
 	ld hl,waitswstr
 	call puts
 	
+	ld c, $07
+	ld a, $07	;start timer, 4.096KHz
+	ld [c], a
+	
 	ld c, $51
 	ld a, $00
 	ld [c],a
 	
+.loop1:
+	push bc
+	call testa
+	pop bc
 	ld c, $51
 	ld b, $0
-.loop1:
 	ld a,[c]
 	cp b
-	jp z,.loop1
+	jr z,.loop1
 .loop2:
 	ld a,[c]
 	cp b
-	jp nz,.loop2
+	jr nz,.loop2
 	ret
 
 waitswstr:
-	db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset.",$0D,$0A,0
+	db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset. Expect A.",$0D,$0A,0
+
+testa:
+	ld c, $0F
+	ld a, [c]
+	ld b, $00
+	cp b
+	ret z
+	xor a
+	ld [c], a
+	ld hl, $D000
+	ld c, [hl]
+	inc bc
+	ld [hl], c
+	ld a, c
+	ld c, $50
+	ld [c], a
+	ret
 
 ; Core instruction basic acceptance tests.
 insntest:
@@ -138,23 +162,23 @@ insntest:
 	ld hl, .pushpopfail
 	ld a, d
 	cp b
-	jp nz,.fail
+	jr nz,.fail
 	ld a, e
 	cp c
-	jp nz,.fail
+	jr nz,.fail
 	
 	; Test ALU (HL).
 	ld hl, .ff
 	ld a, $FF
 	xor [hl]
 	ld hl, .xorhlfail
-	jp nz, .fail
+	jr nz, .fail
 	
 	; Test JP (HL)
 	ld hl, .jphl
 	jp [hl]
 	ld hl, .jphlfail
-	jp .fail
+	jr .fail
 	rst $00
 .jphl:
 
@@ -164,20 +188,32 @@ insntest:
 	cp b
 	jr nz,.jr
 	ld hl, .jrfail
-	jp .fail
+	jr .fail
 	rst $00
 .jr:
+
+	; Test inc16
+	ld d, $12
+	ld e, $FF
+	ld hl, .inc16fail
+	inc de
+	ld a, $13
+	cp d
+	jr nz, .fail
+	ld a, $00
+	cp e
+	jr nz, .fail
 	
 	; Test CP.
 	ld hl, .cpfail
 	ld a, $10
 	ld b, $20
 	cp b
-	jp nc,.fail
+	jr nc,.fail
 	ld a, $20
 	ld b, $10
 	cp b
-	jp c,.fail
+	jr c,.fail
 	
 	; Test CPL
 	ld hl, .cplfail
@@ -185,43 +221,47 @@ insntest:
 	ld b, $AA
 	cpl
 	cp b
-	jp nz,.fail
+	jr nz,.fail
 	
 	ld hl, .ok
 	call puts
 	ret
 .fail:
+	call puts
+	ld hl, .testfailed
 	call puts
 	ret
 .insnteststr:
-	db "Testing instructions... ",$0
+	db "Testing instructions... ",0
 .pushpopfail:
-	db "PUSH/POP test failed.",$0D,$0A,0
+	db "PUSH/POP",0
 .ff:
 	db $FF
 .xorhlfail:
-	db "XOR [HL] test failed.",$0D,$0A,0
+	db "XOR [HL]",0
 .jphlfail:
-	db "JP [HL] test failed.",$0D,$0A,0
+	db "JP [HL]",0
 .jrfail:
-	db "JR test failed.",$0D,$0A,0
+	db "JR",0
 .cpfail:
-	db "CP test failed.",$0D,$0A,0
+	db "CP",0
 .cplfail:
-	db "CPL test failed.",$0D,$0A,0
+	db "CPL",0
+.inc16fail:
+	db "INC16",0
+.testfailed:
+	db " test failed.",$0D,$0A,0
 .ok:
 	db "OK!",$0D,$0A,0
 
 ; Serial port manipulation functions.
 putc:
-	push af
 	ld b, 0
 	ld c, $50
 .waitport:
 	ld a,[c]
 	cp b
-	jp nz,.waitport
-	pop af
+	jr nz,.waitport
 	ld [c],a
 	ret
 
@@ -229,9 +269,6 @@ puts:
 	ld a, [hli]
 	ld b, $00
 	cp b
-	jp z, .done
+	ret z
 	call putc
-	jp puts
-.done:
-	ret
-
+	jr puts