X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/7028b02c470729436badea9acc3224c34621e25a..00573fd53c3dc0b2aca146f085d30801a3aed576:/Makefile diff --git a/Makefile b/Makefile index bf5d698..9d94442 100644 --- a/Makefile +++ b/Makefile @@ -1,16 +1,65 @@ -all: CoreTop.svf +VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \ + insn_jr-jrcc.v insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v \ + insn_ret-retcc.v Interrupt.v Uart.v allinsns.v insn_alu8.v \ + insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v insn_ld_reg_imm16.v \ + insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \ + insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \ + insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \ + Timer.v LCDC.v insn_ldm_a.v -CoreTop_rom.bit: rom.hex CoreTop.bit foo_bd.bmm - data2mem -bm foo_bd.bmm -bd rom.mem -bt CoreTop.bit -o b CoreTop_rom.bit +all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr -CoreTop.svf: CoreTop_rom.bit rom.hex impact.cmd - impact -batch impact.cmd +CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS) + xst -ifn CoreTop.xst -ofn CoreTop.syr -rom.o: rom.asm - rgbasm -orom.o rom.asm +CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf + ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd -rom.bin: rom.o rom.lnk - xlink rom.lnk +CoreTop_map.ncd: CoreTop.ngd + map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf -rom.hex: rom.bin - ./mashrom < rom.bin > rom.hex +CoreTop.ncd: CoreTop_map.ncd + par -w -ol std -t 1 CoreTop_map.ncd CoreTop.ncd CoreTop.pcf + +CoreTop.twr: CoreTop_map.ncd + trce -e 3 -s 5 -xml CoreTop CoreTop.ncd -o CoreTop.twr CoreTop.pcf -ucf CoreTop.ucf + +CoreTop.bit: CoreTop.ut CoreTop.ncd + bitgen -f CoreTop.ut CoreTop.ncd + +netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd + netgen -ise FPGABoy.ise -s 5 -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v + +netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v + vlogcomp netgen/par/CoreTop_timesim.v + vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v + +CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work + fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl + +parsim: CoreTop_isim_par.exe + +%.o: %.asm + rgbasm -o$@ $< + +%.bin: %.o rom.lnk + echo "[Objects]" > tmp.lnk + echo $< >> tmp.lnk + echo "" >> tmp.lnk + echo "[Output]" >> tmp.lnk + echo $@ >> tmp.lnk + xlink tmp.lnk + rm tmp.lnk + +%.mem: %.bin + ./mashrom < $< > $@ + +CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm + data2mem -bm foo_bd.bmm -bd $< -bt CoreTop.bit -o b $@ + +CoreTop_%.svf: CoreTop_%.bit impact.cmd + sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd + impact -batch tmp.cmd + +parsim: CoreTop + \ No newline at end of file