X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/6dbce0b54fbfff7fee918b9033c0111065ce582a..6b4e28281b4fa98272bead1eedeea577e8778169:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 1aaa01c..0697295 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -33,6 +33,20 @@
 `define INSN_LDH_AC			8'b111x0010	// Either LDH A,(C) or LDH (C),A
 `define INSN_LDx_AHL			8'b001xx010	// LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8				8'b10xxxxxx	// 10 xxx yyy
+`define INSN_NOP				8'b00000000
+`define INSN_RST				8'b11xxx111
+`define INSN_RET				8'b110x1001	// 1 = RETI, 0 = RET
+`define INSN_CALL				8'b11001101
+`define INSN_CALLCC			8'b110xx100	// Not that call/cc.
+`define INSN_JP_imm			8'b11000011
+`define INSN_JPCC_imm		8'b110xx010
+`define INSN_ALU_A		8'b00xxx111
+`define INSN_JP_HL			8'b11101001
+
+`define INSN_cc_NZ			2'b00
+`define INSN_cc_Z				2'b01
+`define INSN_cc_NC			2'b10
+`define INSN_cc_C				2'b11
 
 `define INSN_reg_A		3'b111
 `define INSN_reg_B		3'b000
@@ -58,6 +72,14 @@
 `define INSN_alu_XOR		3'b101
 `define INSN_alu_OR		3'b110
 `define INSN_alu_CP		3'b111		// Oh lawd, is dat some CP?
+`define INSN_alu_RLCA		3'b000
+`define INSN_alu_RRCA		3'b001
+`define INSN_alu_RLA		3'b010
+`define INSN_alu_RRA		3'b011
+`define INSN_alu_DAA		3'b100
+`define INSN_alu_CPL		3'b101
+`define INSN_alu_SCF		3'b110
+`define INSN_alu_CCF		3'b111
 
 module GBZ80Core(
 	input clk,
@@ -77,11 +99,13 @@ module GBZ80Core(
 	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
 	reg rd = 1, wr = 0, newcycle = 1;
 	
-	reg [7:0] tmp;					/* Generic temporary reg. */
+	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
 	
 	reg [7:0] buswdata;
 	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
 	
+	reg ie = 0;
+	
 	initial begin
 		registers[ 0] <= 0;
 		registers[ 1] <= 0;
@@ -95,19 +119,28 @@ module GBZ80Core(
 		registers[ 9] <= 0;
 		registers[10] <= 0;
 		registers[11] <= 0;
+		ie <= 0;
+		rd <= 1;
+		wr <= 0;
+		newcycle <= 1;
+		state <= 0;
+		cycle <= 0;
 	end
 
 	always @(posedge clk)
 		case (state)
 		`STATE_FETCH: begin
-			if (wr)
-				buswdata <= wdata;
-			if (newcycle)
+			if (newcycle) begin
 				busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
-			else
+				buswr <= 0;
+				busrd <= 1;
+			end else begin
 				busaddress <= address;
-			buswr <= wr;
-			busrd <= rd;
+				buswr <= wr;
+				busrd <= rd;
+				if (wr)
+					buswdata <= wdata;
+			end
 			state <= `STATE_DECODE;
 		end
 		`STATE_DECODE: begin
@@ -116,8 +149,10 @@ module GBZ80Core(
 				rdata <= busdata;
 				newcycle <= 0;
 				cycle <= 0;
-			end else
+			end else begin
 				if (rd) rdata <= busdata;
+				cycle <= cycle + 1;
+			end
 			buswr <= 0;
 			busrd <= 0;
 			wr <= 0;
@@ -141,7 +176,7 @@ module GBZ80Core(
 						`EXEC_NEXTADDR_PCINC;
 						rd <= 1;
 					end
-				1: begin
+				1:	begin
 						`EXEC_INC_PC;
 						if (opcode[5:3] == `INSN_reg_dHL) begin
 							address <= {registers[`REG_H], registers[`REG_L]};
@@ -152,7 +187,7 @@ module GBZ80Core(
 							`EXEC_NEWCYCLE;
 						end
 					end
-				2: begin
+				2:	begin
 						`EXEC_NEWCYCLE;
 					end
 				endcase
@@ -165,13 +200,13 @@ module GBZ80Core(
 				case (cycle)
 				0:	begin
 						case (opcode[2:0])
-						`INSN_reg_A:	begin wdata <= registers[`REG_A]; end
-						`INSN_reg_B:	begin wdata <= registers[`REG_B]; end
-						`INSN_reg_C:	begin wdata <= registers[`REG_C]; end
-						`INSN_reg_D:	begin wdata <= registers[`REG_D]; end
-						`INSN_reg_E:	begin wdata <= registers[`REG_E]; end
-						`INSN_reg_H:	begin wdata <= registers[`REG_H]; end
-						`INSN_reg_L:	begin wdata <= registers[`REG_L]; end
+						`INSN_reg_A:	wdata <= registers[`REG_A];
+						`INSN_reg_B:	wdata <= registers[`REG_B];
+						`INSN_reg_C:	wdata <= registers[`REG_C];
+						`INSN_reg_D:	wdata <= registers[`REG_D];
+						`INSN_reg_E:	wdata <= registers[`REG_E];
+						`INSN_reg_H:	wdata <= registers[`REG_H];
+						`INSN_reg_L:	wdata <= registers[`REG_L];
 						endcase
 						address <= {registers[`REG_H], registers[`REG_L]};
 						wr <= 1; rd <= 0;
@@ -184,11 +219,11 @@ module GBZ80Core(
 			end
 			`INSN_LD_reg_HL: begin
 				case(cycle)
-				0: begin
+				0:	begin
 						address <= {registers[`REG_H], registers[`REG_L]};
 						rd <= 1;
 					end
-				1: begin
+				1:	begin
 						tmp <= rdata;
 						`EXEC_INC_PC;
 						`EXEC_NEWCYCLE;
@@ -199,13 +234,13 @@ module GBZ80Core(
 				`EXEC_INC_PC;
 				`EXEC_NEWCYCLE;
 				case (opcode[2:0])
-				`INSN_reg_A:	begin tmp <= registers[`REG_A]; end
-				`INSN_reg_B:	begin tmp <= registers[`REG_B]; end
-				`INSN_reg_C:	begin tmp <= registers[`REG_C]; end
-				`INSN_reg_D:	begin tmp <= registers[`REG_D]; end
-				`INSN_reg_E:	begin tmp <= registers[`REG_E]; end
-				`INSN_reg_H:	begin tmp <= registers[`REG_H]; end
-				`INSN_reg_L:	begin tmp <= registers[`REG_L]; end
+				`INSN_reg_A:	tmp <= registers[`REG_A];
+				`INSN_reg_B:	tmp <= registers[`REG_B];
+				`INSN_reg_C:	tmp <= registers[`REG_C];
+				`INSN_reg_D:	tmp <= registers[`REG_D];
+				`INSN_reg_E:	tmp <= registers[`REG_E];
+				`INSN_reg_H:	tmp <= registers[`REG_H];
+				`INSN_reg_L:	tmp <= registers[`REG_L];
 				endcase
 			end
 			`INSN_LD_reg_imm16: begin
@@ -236,7 +271,7 @@ module GBZ80Core(
 			end
 			`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
 				case (cycle)
-				0: begin
+				0:	begin
 						wr <= 1;
 						address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
 						case (opcode[5:4])
@@ -246,7 +281,7 @@ module GBZ80Core(
 						`INSN_stack_HL:	wdata <= registers[`REG_H];
 						endcase
 					end
-				1: begin
+				1:	begin
 						wr <= 1;
 						address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
 						case (opcode[5:4])
@@ -256,8 +291,8 @@ module GBZ80Core(
 						`INSN_stack_HL:	wdata <= registers[`REG_L];
 						endcase
 					end
-				2:	begin /* TWIDDLE OUR FUCKING THUMBS! */ end
-				3: begin
+				2:	begin /* Twiddle thumbs. */ end
+				3:	begin
 						`EXEC_NEWCYCLE;
 						`EXEC_INC_PC;
 					end
@@ -265,15 +300,15 @@ module GBZ80Core(
 			end
 			`INSN_POP_reg: begin	/* POP is 12 cycles! */
 				case (cycle)
-				0: begin
+				0:	begin
 						rd <= 1;
 						address <= {registers[`REG_SPH],registers[`REG_SPL]};
 					end
-				1: begin
+				1:	begin
 						rd <= 1;
 						address <= {registers[`REG_SPH],registers[`REG_SPL]};
 					end
-				2: begin
+				2:	begin
 						`EXEC_NEWCYCLE;
 						`EXEC_INC_PC;
 					end
@@ -290,7 +325,7 @@ module GBZ80Core(
 							wdata <= registers[`REG_A];
 						end
 					end
-				1: begin
+				1:	begin
 						`EXEC_NEWCYCLE;
 						`EXEC_INC_PC;
 					end
@@ -298,7 +333,7 @@ module GBZ80Core(
 			end
 			`INSN_LDx_AHL: begin
 				case (cycle)
-				0: begin
+				0:	begin
 						address <= {registers[`REG_H],registers[`REG_L]};
 						if (opcode[3]) begin	// LDx A, (HL)
 							rd <= 1;
@@ -322,17 +357,134 @@ module GBZ80Core(
 					`EXEC_NEWCYCLE;
 					`EXEC_INC_PC;
 					case (opcode[2:0])
-					`INSN_reg_A:	begin tmp <= registers[`REG_A]; end
-					`INSN_reg_B:	begin tmp <= registers[`REG_B]; end
-					`INSN_reg_C:	begin tmp <= registers[`REG_C]; end
-					`INSN_reg_D:	begin tmp <= registers[`REG_D]; end
-					`INSN_reg_E:	begin tmp <= registers[`REG_E]; end
-					`INSN_reg_H:	begin tmp <= registers[`REG_H]; end
-					`INSN_reg_L:	begin tmp <= registers[`REG_L]; end
-					`INSN_reg_dHL:	begin tmp <= rdata; end
+					`INSN_reg_A:	tmp <= registers[`REG_A];
+					`INSN_reg_B:	tmp <= registers[`REG_B];
+					`INSN_reg_C:	tmp <= registers[`REG_C];
+					`INSN_reg_D:	tmp <= registers[`REG_D];
+					`INSN_reg_E:	tmp <= registers[`REG_E];
+					`INSN_reg_H:	tmp <= registers[`REG_H];
+					`INSN_reg_L:	tmp <= registers[`REG_L];
+					`INSN_reg_dHL:	tmp <= rdata;
 					endcase
 				end
 			end
+			`INSN_ALU_A: begin
+				`EXEC_NEWCYCLE;
+				`EXEC_INC_PC;
+			end
+			`INSN_NOP: begin
+				`EXEC_NEWCYCLE;
+				`EXEC_INC_PC;
+			end
+			`INSN_RST: begin
+				case (cycle)
+				0:	begin
+						`EXEC_INC_PC;		// This goes FIRST in RST
+					end
+				1:	begin
+						wr <= 1;
+						address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+						wdata <= registers[`REG_PCH];
+					end
+				2:	begin
+						wr <= 1;
+						address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
+						wdata <= registers[`REG_PCL];
+					end
+				3:	begin
+						`EXEC_NEWCYCLE;
+						{registers[`REG_PCH],registers[`REG_PCL]} <=
+							{10'b0,opcode[5:3],3'b0};
+					end
+				endcase
+			end
+			`INSN_RET: begin
+				case (cycle)
+				0:	begin
+						rd <= 1;
+						address <= {registers[`REG_SPH],registers[`REG_SPL]};
+					end
+				1:	begin
+						rd <= 1;
+						address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+					end
+				2:	begin /* twiddle thumbs */ end
+				3:	begin
+						`EXEC_NEWCYCLE;
+						// do NOT increment PC!
+					end
+				endcase
+			end
+			`INSN_CALL,`INSN_CALLCC: begin
+				case (cycle)
+				0:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				1:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				2:	begin
+						`EXEC_INC_PC;
+						if (!opcode[0])	// i.e., is callcc
+							/* We need to check the condition code to bail out. */
+							case (opcode[4:3])
+							`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+							endcase
+					end
+				3:	begin
+						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+						wdata <= registers[`REG_PCH];
+						wr <= 1;
+					end
+				4:	begin
+						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+						wdata <= registers[`REG_PCL];
+						wr <= 1;
+					end
+				5:	begin
+						`EXEC_NEWCYCLE;	/* do NOT increment the PC */
+					end
+				endcase
+			end
+			`INSN_JP_imm,`INSN_JPCC_imm: begin
+				case (cycle)
+				0:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				1:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				2:	begin
+						`EXEC_INC_PC;
+						if (!opcode[0]) begin	// i.e., JP cc,nn
+							/* We need to check the condition code to bail out. */
+							case (opcode[4:3])
+							`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+							endcase
+						end
+					end
+				3:	begin
+						`EXEC_NEWCYCLE;
+					end
+				endcase
+			end
+			`INSN_JP_HL: begin
+				`EXEC_NEWCYCLE;
+			end
 			default:
 				$stop;
 			endcase
@@ -342,60 +494,56 @@ module GBZ80Core(
 			casex (opcode)
 			`INSN_LD_reg_imm8:
 				case (cycle)
-				0: cycle <= 1;
-				1: case (opcode[5:3])
-					`INSN_reg_A:	begin registers[`REG_A] <= rdata; cycle <= 0; end
-					`INSN_reg_B:	begin registers[`REG_B] <= rdata; cycle <= 0; end
-					`INSN_reg_C:	begin registers[`REG_C] <= rdata; cycle <= 0; end
-					`INSN_reg_D:	begin registers[`REG_D] <= rdata; cycle <= 0; end
-					`INSN_reg_E:	begin registers[`REG_E] <= rdata; cycle <= 0; end
-					`INSN_reg_H:	begin registers[`REG_H] <= rdata; cycle <= 0; end
-					`INSN_reg_L:	begin registers[`REG_L] <= rdata; cycle <= 0; end
-					`INSN_reg_dHL:	cycle <= 2;
+				0:	begin end
+				1:	case (opcode[5:3])
+					`INSN_reg_A:	begin registers[`REG_A] <= rdata; end
+					`INSN_reg_B:	begin registers[`REG_B] <= rdata; end
+					`INSN_reg_C:	begin registers[`REG_C] <= rdata; end
+					`INSN_reg_D:	begin registers[`REG_D] <= rdata; end
+					`INSN_reg_E:	begin registers[`REG_E] <= rdata; end
+					`INSN_reg_H:	begin registers[`REG_H] <= rdata; end
+					`INSN_reg_L:	begin registers[`REG_L] <= rdata; end
+					`INSN_reg_dHL:	begin /* Go off to cycle 2 */ end
 					endcase
-				2: cycle <= 0;
+				2:	begin end
 				endcase
 			`INSN_HALT: begin
 				/* Nothing needs happen here. */
 				/* XXX Interrupts needed for HALT. */
 			end
 			`INSN_LD_HL_reg: begin
-				case (cycle)
-				0: cycle <= 1;
-				1: cycle <= 0;
-				endcase
+				/* Nothing of interest here */
 			end
 			`INSN_LD_reg_HL: begin
 				case (cycle)
-				0:	cycle <= 1;
+				0:	begin end
 				1:	begin
 						case (opcode[5:3])
-						`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
-						`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
-						`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
-						`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
-						`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
-						`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
-						`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
+						`INSN_reg_A:	registers[`REG_A] <= tmp;
+						`INSN_reg_B:	registers[`REG_B] <= tmp;
+						`INSN_reg_C:	registers[`REG_C] <= tmp;
+						`INSN_reg_D:	registers[`REG_D] <= tmp;
+						`INSN_reg_E:	registers[`REG_E] <= tmp;
+						`INSN_reg_H:	registers[`REG_H] <= tmp;
+						`INSN_reg_L:	registers[`REG_L] <= tmp;
 						endcase
-						cycle <= 0;
 					end
 				endcase
 			end
 			`INSN_LD_reg_reg: begin
 				case (opcode[5:3])
-				`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
-				`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
-				`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
-				`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
-				`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
-				`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
-				`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
+				`INSN_reg_A:	registers[`REG_A] <= tmp;
+				`INSN_reg_B:	registers[`REG_B] <= tmp;
+				`INSN_reg_C:	registers[`REG_C] <= tmp;
+				`INSN_reg_D:	registers[`REG_D] <= tmp;
+				`INSN_reg_E:	registers[`REG_E] <= tmp;
+				`INSN_reg_H:	registers[`REG_H] <= tmp;
+				`INSN_reg_L:	registers[`REG_L] <= tmp;
 				endcase
 			end
 			`INSN_LD_reg_imm16: begin
 				case (cycle)
-				0:	cycle <= 1;
+				0:	begin /* */ end
 				1:	begin
 						case (opcode[5:4])
 						`INSN_reg16_BC:	registers[`REG_C] <= rdata;
@@ -403,7 +551,6 @@ module GBZ80Core(
 						`INSN_reg16_HL:	registers[`REG_L] <= rdata;
 						`INSN_reg16_SP:	registers[`REG_SPL] <= rdata;
 						endcase
-						cycle <= 2;
 					end
 				2: begin
 						case (opcode[5:4])
@@ -412,45 +559,29 @@ module GBZ80Core(
 						`INSN_reg16_HL:	registers[`REG_H] <= rdata;
 						`INSN_reg16_SP:	registers[`REG_SPH] <= rdata;
 						endcase
-						cycle <= 0;
 					end
 				endcase
 			end
 			`INSN_LD_SP_HL: begin
 				case (cycle)
-				0: begin
-						cycle <= 1;
-						registers[`REG_SPH] <= tmp;
-					end
-				1: begin
-						cycle <= 0;
-						registers[`REG_SPL] <= tmp;
-					end
+				0:	registers[`REG_SPH] <= tmp;
+				1: registers[`REG_SPL] <= tmp;
 				endcase
 			end
 			`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
 				case (cycle)
-				0: begin
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} - 1;
-						cycle <= 1;
-					end
-				1:	begin
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} - 1;
-						cycle <= 2;
-					end
-				2:	cycle <= 3;
-				3:	cycle <= 0;
+				0:	{registers[`REG_SPH],registers[`REG_SPL]} <=
+						{registers[`REG_SPH],registers[`REG_SPL]} - 1;
+				1:	{registers[`REG_SPH],registers[`REG_SPL]} <=
+						{registers[`REG_SPH],registers[`REG_SPL]} - 1;
+				2:	begin /* type F */ end
+				3:	begin /* type F */ end
 				endcase
 			end
 			`INSN_POP_reg: begin	/* POP is 12 cycles! */
 				case (cycle)
-				0:	begin
-						cycle <= 1;
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} + 1;
-					end
+				0:	{registers[`REG_SPH],registers[`REG_SPL]} <=
+						{registers[`REG_SPH],registers[`REG_SPL]} + 1;
 				1:	begin
 						case (opcode[5:4])
 						`INSN_stack_AF:	registers[`REG_F] <= rdata;
@@ -460,7 +591,6 @@ module GBZ80Core(
 						endcase
 						{registers[`REG_SPH],registers[`REG_SPL]} <=
 							{registers[`REG_SPH],registers[`REG_SPL]} + 1;
-						cycle <= 2;
 					end
 				2:	begin
 						case (opcode[5:4])
@@ -469,25 +599,20 @@ module GBZ80Core(
 						`INSN_stack_DE:	registers[`REG_D] <= rdata;
 						`INSN_stack_HL:	registers[`REG_H] <= rdata;
 						endcase
-						cycle <= 0;
 					end
 				endcase
 			end
 			`INSN_LDH_AC: begin
 				case (cycle)
-				0:	cycle <= 1;
-				1: begin
-						cycle <= 0;
-						if (opcode[4])
-							registers[`REG_A] <= rdata;
-					end
+				0:	begin /* Type F */ end
+				1:	if (opcode[4])
+						registers[`REG_A] <= rdata;
 				endcase
 			end
 			`INSN_LDx_AHL: begin
 				case (cycle)
-				0:	cycle <= 1;
+				0:	begin /* Type F */ end
 				1:	begin
-						cycle <= 0;
 						if (opcode[3])
 							registers[`REG_A] <= rdata;
 						{registers[`REG_H],registers[`REG_L]} <=
@@ -500,7 +625,6 @@ module GBZ80Core(
 			`INSN_ALU8: begin
 				if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
 					/* Sit on our asses. */
-					cycle <= 1;
 				end else begin		/* Actually do the computation! */
 					case (opcode[5:3])
 					`INSN_alu_ADD: begin
@@ -508,7 +632,7 @@ module GBZ80Core(
 							registers[`REG_A] + tmp;
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
-							  /* N */ 0,
+							  /* N */ 1'b0,
 							  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
 							  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
 							  registers[`REG_F][3:0]
@@ -519,18 +643,40 @@ module GBZ80Core(
 							registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
-							  /* N */ 0,
+							  /* N */ 1'b0,
 							  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
 							  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
 							  registers[`REG_F][3:0]
 							};
 					end
+					`INSN_alu_SUB: begin
+						registers[`REG_A] <=
+							registers[`REG_A] - tmp;
+						registers[`REG_F] <=
+							{ /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+							  /* N */ 1'b1,
+							  /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+							  /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+							  registers[`REG_F][3:0]
+							};
+					end
+					`INSN_alu_SBC: begin
+						registers[`REG_A] <=
+							registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
+						registers[`REG_F] <=
+							{ /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+							  /* N */ 1'b1,
+							  /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
+							  /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
+							  registers[`REG_F][3:0]
+							};
+					end
 					`INSN_alu_AND: begin
 						registers[`REG_A] <=
 							registers[`REG_A] & tmp;
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
-							  0,1,0,
+							  3'b010,
 							  registers[`REG_F][3:0]
 							};
 					end
@@ -539,7 +685,7 @@ module GBZ80Core(
 							registers[`REG_A] | tmp;
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
-							  0,0,0,
+							  3'b000,
 							  registers[`REG_F][3:0]
 							};
 					end
@@ -548,7 +694,16 @@ module GBZ80Core(
 							registers[`REG_A] ^ tmp;
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
-							  0,0,0,
+							  3'b000,
+							  registers[`REG_F][3:0]
+							};
+					end
+					`INSN_alu_CP: begin
+						registers[`REG_F] <=
+							{ /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+							  /* N */ 1'b1,
+							  /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+							  /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
 							  registers[`REG_F][3:0]
 							};
 					end
@@ -557,27 +712,90 @@ module GBZ80Core(
 					endcase
 				end
 			end
+			`INSN_ALU_A: begin
+				case(opcode[5:3])
+				`INSN_alu_RLCA: begin
+					registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
+					registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+				end
+				`INSN_alu_RRCA: begin
+					registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
+					registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+				end
+				`INSN_alu_RLA: begin
+					registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
+					registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+				end
+				`INSN_alu_RRA: begin
+					registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
+					registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+				end
+				`INSN_alu_CPL: begin
+					registers[`REG_A] <= ~registers[`REG_A];
+					registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
+				end
+				`INSN_alu_SCF: begin
+					registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
+				end
+				`INSN_alu_CCF: begin
+					registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
+				end
+				endcase
+			end
+			`INSN_NOP: begin /* NOP! */ end
+			`INSN_RST: begin
+				case (cycle)
+				0:	begin /* type F */ end
+				1:	begin /* type F */ end
+				2:	begin /* type F */ end
+				3:	{registers[`REG_SPH],registers[`REG_SPL]} <=
+						{registers[`REG_SPH],registers[`REG_SPL]}-2;
+				endcase
+			end
+			`INSN_RET: begin
+				case (cycle)
+				0:	begin /* type F */ end
+				1:	registers[`REG_PCL] <= rdata;
+				2:	registers[`REG_PCH] <= rdata;
+				3:	begin
+						{registers[`REG_SPH],registers[`REG_SPL]} <=
+							{registers[`REG_SPH],registers[`REG_SPL]} + 2;
+						if (opcode[4])	/* RETI */
+							ie <= 1;
+					end
+				endcase
+			end
+			`INSN_CALL,`INSN_CALLCC: begin
+				case (cycle)
+				0:	begin /* type F */ end
+				1:	tmp <= rdata;	// tmp contains newpcl
+				2:	tmp2 <= rdata;	// tmp2 contains newpch
+				3:	begin /* type F */ end
+				4:	registers[`REG_PCH] <= tmp2;
+				5: begin
+						{registers[`REG_SPH],registers[`REG_SPL]} <=
+							{registers[`REG_SPH],registers[`REG_SPL]} - 2;
+						registers[`REG_PCL] <= tmp;
+					end
+				endcase
+			end
+			`INSN_JP_imm,`INSN_JPCC_imm: begin
+				case (cycle)
+				0:	begin /* type F */ end
+				1:	tmp <= rdata;	// tmp contains newpcl
+				2:	tmp2 <= rdata;	// tmp2 contains newpch
+				3:	{registers[`REG_PCH],registers[`REG_PCL]} <=
+						{tmp2,tmp};
+				endcase
+			end
+			`INSN_JP_HL: begin
+				{registers[`REG_PCH],registers[`REG_PCL]} <=
+					{registers[`REG_H],registers[`REG_L]};
+			end
+			default:
+				$stop;
 			endcase
 			state <= `STATE_FETCH;
 		end
 		endcase
 endmodule
-
-`timescale 1ns / 1ps
-module TestBench();
-	reg clk = 0;
-	wire [15:0] addr;
-	wire [7:0] data;
-	wire wr, rd;
-	reg [7:0] rom [2047:0];
-	
-	initial $readmemh("rom.hex", rom);
-	always #10 clk <= ~clk;
-	GBZ80Core core(
-		.clk(clk),
-		.busaddress(addr),
-		.busdata(data),
-		.buswr(wr),
-		.busrd(rd));
-	assign data = rd ? rom[addr] : 8'bzzzzzzzz;
-endmodule