X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/6c46357c6f1bfeefc3a9f85aed03f94e923d09f1..ee31adcb22c5011aeaaa0149ee22fa18e45317a5:/Makefile

diff --git a/Makefile b/Makefile
index 41aff51..cf89f73 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,8 @@ VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
 	insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \
 	insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
 	insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
-	Timer.v
+	Timer.v LCDC.v insn_ldm8_a.v insn_ldm16_a.v Framebuffer.v \
+	insn_ldbcde_a.v
 
 all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr
 
@@ -27,10 +28,22 @@ CoreTop.twr: CoreTop_map.ncd
 CoreTop.bit: CoreTop.ut CoreTop.ncd
 	bitgen -f CoreTop.ut CoreTop.ncd
 
+netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
+	netgen -ise FPGABoy.ise -s 5  -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
+
+netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
+	vlogcomp netgen/par/CoreTop_timesim.v
+	vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
+	
+CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
+	fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
+
+parsim: CoreTop_isim_par.exe
+
 %.o: %.asm
 	rgbasm -o$@ $<
 
-%.bin: %.o rom.lnk
+%.bin: %.o
 	echo "[Objects]" > tmp.lnk
 	echo $< >> tmp.lnk
 	echo "" >> tmp.lnk
@@ -39,7 +52,7 @@ CoreTop.bit: CoreTop.ut CoreTop.ncd
 	xlink tmp.lnk
 	rm tmp.lnk
 
-%.mem: %.bin
+%.mem: %.bin mashrom
 	./mashrom < $< > $@
 
 CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
@@ -48,3 +61,6 @@ CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
 CoreTop_%.svf: CoreTop_%.bit impact.cmd
 	sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
 	impact -batch tmp.cmd
+
+parsim: CoreTop
+	
\ No newline at end of file