X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/6c46357c6f1bfeefc3a9f85aed03f94e923d09f1..91c74a3f7409b5ac9bdbd46fbff13c513b19bc9c:/GBZ80Core.v?ds=inline diff --git a/GBZ80Core.v b/GBZ80Core.v index 36cd76a..ec882da 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -40,34 +40,45 @@ `define STATE_EXECUTE 2'h2 `define STATE_WRITEBACK 2'h3 -`define INSN_LD_reg_imm8 8'b00xxx110 -`define INSN_HALT 8'b01110110 -`define INSN_LD_HL_reg 8'b01110xxx -`define INSN_LD_reg_HL 8'b01xxx110 -`define INSN_LD_reg_reg 8'b01xxxxxx -`define INSN_LD_reg_imm16 8'b00xx0001 -`define INSN_LD_SP_HL 8'b11111001 -`define INSN_PUSH_reg 8'b11xx0101 -`define INSN_POP_reg 8'b11xx0001 -`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A -`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A -`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy -`define INSN_NOP 8'b00000000 -`define INSN_RST 8'b11xxx111 -`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET -`define INSN_RETCC 8'b110xx000 -`define INSN_CALL 8'b11001101 -`define INSN_CALLCC 8'b110xx100 // Not that call/cc. -`define INSN_JP_imm 8'b11000011 -`define INSN_JPCC_imm 8'b110xx010 -`define INSN_ALU_A 8'b00xxx111 -`define INSN_JP_HL 8'b11101001 -`define INSN_JR_imm 8'b00011000 -`define INSN_JRCC_imm 8'b001xx000 -`define INSN_INCDEC16 8'b00xxx011 -`define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending. -`define INSN_DI 8'b11110011 -`define INSN_EI 8'b11111011 +`define INSN_LD_reg_imm8 9'b000xxx110 +`define INSN_HALT 9'b001110110 +`define INSN_LD_HL_reg 9'b001110xxx +`define INSN_LD_reg_HL 9'b001xxx110 +`define INSN_LD_reg_reg 9'b001xxxxxx +`define INSN_LD_reg_imm16 9'b000xx0001 +`define INSN_LD_SP_HL 9'b011111001 +`define INSN_PUSH_reg 9'b011xx0101 +`define INSN_POP_reg 9'b011xx0001 +`define INSN_LDH_AC 9'b0111x0010 // Either LDH A,(C) or LDH (C),A +`define INSN_LDx_AHL 9'b0001xx010 // LDD/LDI A,(HL) / (HL),A +`define INSN_ALU8 9'b010xxxxxx // 10 xxx yyy +`define INSN_ALU8IMM 9'b011xxx110 +`define INSN_NOP 9'b000000000 +`define INSN_RST 9'b011xxx111 +`define INSN_RET 9'b0110x1001 // 1 = RETI, 0 = RET +`define INSN_RETCC 9'b0110xx000 +`define INSN_CALL 9'b011001101 +`define INSN_CALLCC 9'b0110xx100 // Not that call/cc. +`define INSN_JP_imm 9'b011000011 +`define INSN_JPCC_imm 9'b0110xx010 +`define INSN_ALU_A 9'b000xxx111 +`define INSN_JP_HL 9'b011101001 +`define INSN_JR_imm 9'b000011000 +`define INSN_JRCC_imm 9'b0001xx000 +`define INSN_INCDEC16 9'b000xxx011 +`define INSN_VOP_INTR 9'b011111100 // 0xFC is grabbed by the fetch if there is an interrupt pending. +`define INSN_DI 9'b011110011 +`define INSN_EI 9'b011111011 +`define INSN_INCDEC_HL 9'b00011010x +`define INSN_INCDEC_reg8 9'b000xxx10x +`define INSN_LD8M_A 9'b0111x0000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 +`define INSN_LD16M_A 9'b0111x1010 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 +`define INSN_LDBCDE_A 9'b0000xx010 +`define INSN_TWO_BYTE 9'b011001011 // prefix for two-byte opqodes +`define INSN_ALU_EXT 9'b100xxxxxx +`define INSN_BIT 9'b101xxxxxx +`define INSN_RES 9'b110xxxxxx +`define INSN_SET 9'b111xxxxxx `define INSN_cc_NZ 2'b00 `define INSN_cc_Z 2'b01 @@ -106,21 +117,44 @@ `define INSN_alu_CPL 3'b101 `define INSN_alu_SCF 3'b110 `define INSN_alu_CCF 3'b111 +`define INSN_alu_RLC 3'b000 +`define INSN_alu_RRC 3'b001 +`define INSN_alu_RL 3'b010 +`define INSN_alu_RR 3'b011 +`define INSN_alu_DA_SLA 3'b100 +`define INSN_alu_CPL_SRA 3'b101 +`define INSN_alu_SCF_SWAP 3'b110 +`define INSN_alu_CCF_SRL 3'b111 `define EXEC_INC_PC `_PC <= `_PC + 1; `define EXEC_NEXTADDR_PCINC address <= `_PC + 1; `define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end -`define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end -`define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end +`define EXEC_NEWCYCLE_TWOBYTE begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end +`ifdef verilator + `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end + `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end +`else + `ifdef isim + `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end + `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end + `else +/* Work around XST's retarded bugs :\ */ + `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end + `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end + `endif +`endif module GBZ80Core( input clk, - output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */ - inout [7:0] busdata, - output reg buswr, output reg busrd, + inout [15:0] bus0address, /* BUS_* is latched on STATE_FETCH. */ + inout [7:0] bus0data, + inout bus0wr, bus0rd, + inout [15:0] bus1address, /* BUS_* is latched on STATE_FETCH. */ + inout [7:0] bus1data, + inout bus1wr, bus1rd, input irq, input [7:0] jaddr, output reg [1:0] state); - + // reg [1:0] state; /* State within this bus cycle (see STATE_*). */ reg [2:0] cycle; /* Cycle for instructions. */ @@ -128,31 +162,107 @@ module GBZ80Core( reg [15:0] address; /* Address for the next bus operation. */ - reg [7:0] opcode; /* Opcode from the current machine cycle. */ - + reg [8:0] opcode; /* Opcode from the current machine cycle. */ + reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */ - reg rd, wr, newcycle; + reg rd, wr, newcycle, twobyte; reg [7:0] tmp, tmp2; /* Generic temporary regs. */ reg [7:0] buswdata; - assign busdata = buswr ? buswdata : 8'bzzzzzzzz; + wire [7:0] busdata; - reg ie, iedelay; + reg [15:0] busaddress; + reg buswr, busrd; + reg bootstrap_enb; + + wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF)); /* 0 or 1 depending on which bus */ + + assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz; + assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz; + assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz; + assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz; + assign busdata = (bus == 0) ? bus0data : bus1data; + assign bus0rd = (bus == 0) ? busrd : 1'bz; + assign bus1rd = (bus == 1) ? busrd : 1'bz; + assign bus0wr = (bus == 0) ? buswr : 1'bz; + assign bus1wr = (bus == 1) ? buswr : 1'bz; + + reg ie, iedelay; + + wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl; + wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf; + wire [7:0] alu_res; + wire [3:0] f_res; + + assign rlc = {tmp[6:0],tmp[7]}; + assign rlcf = {(tmp == 0 ? 1'b1 : 1'b0) + ,2'b0, + tmp[7]}; + + assign rrc = {tmp[0],tmp[7:1]}; + assign rrcf = {(tmp == 0 ? 1'b1 : 1'b0), + 2'b0, + tmp[0]}; + + assign rl = {tmp[6:0],`_F[4]}; + assign rlf = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0), + 2'b0, + tmp[7]}; + + assign rr = {`_F[4],tmp[7:1]}; + assign rrf = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0), + 2'b0, + tmp[0]}; + + assign sla = {tmp[6:0],1'b0}; + assign slaf = {(tmp[6:0] == 0 ? 1'b1 : 1'b0), + 2'b0, + tmp[7]}; + + assign sra = {tmp[7],tmp[7:1]}; +// assign sraf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]}; now in assign srlf = + + assign swap = {tmp[3:0],tmp[7:4]}; + assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0), + 3'b0}; + + assign srl = {1'b0,tmp[7:1]}; + assign srlf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0), + 2'b0, + tmp[0]}; + assign sraf = srlf; + + /* Y U Q */ + assign {alu_res,f_res} = + opcode[5] ? ( + opcode[4] ? ( + opcode[3] ? {srl,srlf} : {swap,swapf} + ) : ( + opcode[3] ? {sra,sraf} : {sla,slaf} + ) + ) : ( + opcode[4] ? ( + opcode[3] ? {rr,rrf} : {rl,rlf} + ) : ( + opcode[3] ? {rrc,rrcf} : {rlc,rlcf} + ) + ); + initial begin - registers[ 0] <= 0; - registers[ 1] <= 0; - registers[ 2] <= 0; - registers[ 3] <= 0; - registers[ 4] <= 0; - registers[ 5] <= 0; - registers[ 6] <= 0; - registers[ 7] <= 0; - registers[ 8] <= 0; - registers[ 9] <= 0; - registers[10] <= 0; - registers[11] <= 0; + `_A <= 0; + `_B <= 0; + `_C <= 0; + `_D <= 0; + `_E <= 0; + `_F <= 0; + `_H <= 0; + `_L <= 0; + `_PCH <= 0; + `_PCL <= 0; + `_SPH <= 0; + `_SPL <= 0; rd <= 1; wr <= 0; newcycle <= 1; @@ -166,13 +276,15 @@ module GBZ80Core( opcode <= 0; state <= `STATE_WRITEBACK; cycle <= 0; + twobyte <= 0; + bootstrap_enb <= 1; end always @(posedge clk) case (state) `STATE_FETCH: begin if (newcycle) begin - busaddress <= {registers[`REG_PCH], registers[`REG_PCL]}; + busaddress <= `_PC; buswr <= 0; busrd <= 1; end else begin @@ -186,10 +298,13 @@ module GBZ80Core( end `STATE_DECODE: begin if (newcycle) begin - if (ie && irq) + if (twobyte) begin + opcode <= {1'b1,busdata}; + twobyte <= 0; + end else if (ie && irq) opcode <= `INSN_VOP_INTR; else - opcode <= busdata; + opcode <= {1'b0,busdata}; rdata <= busdata; newcycle <= 0; cycle <= 0;