X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/6c46357c6f1bfeefc3a9f85aed03f94e923d09f1..179b434745a7b2da871d69c201dd1bda3e445f41:/System.v

diff --git a/System.v b/System.v
index 4081771..00ee4ec 100644
--- a/System.v
+++ b/System.v
@@ -73,7 +73,8 @@ module CoreTop(
 	CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
 	
 	wire cclk;
-	IBUFG ibuf (.O(cclk), .I(switches[0]));
+//	IBUFG ibuf (.O(cclk), .I(switches[0] & clk));
+	assign cclk = clk;
 
 	wire [15:0] addr;	
 	wire [7:0] data;
@@ -82,9 +83,9 @@ module CoreTop(
 	wire irq, tmrirq;
 	wire [7:0] jaddr;
 	wire [1:0] state;
-
+	
 	GBZ80Core core(
-		.clk(cclk),
+		.clk(clk),
 		.busaddress(addr),
 		.busdata(data),
 		.buswr(wr),
@@ -107,10 +108,10 @@ module CoreTop(
 		.out(seven),
 		.freeze(buttons[0]),
 		.periods(
-			(state == 2'b00) ? 4'b1000 :
-			(state == 2'b01) ? 4'b0100 :
-			(state == 2'b10) ? 4'b0010 :
-			                   4'b0001) );
+			(state == 2'b00) ? 4'b0010 :
+			(state == 2'b01) ? 4'b0001 :
+			(state == 2'b10) ? 4'b1000 :
+			                   4'b0100) );
 	 
 	Switches sw(
 		.address(addr),
@@ -175,7 +176,7 @@ module TestBench();
 	wire [7:0] leds;
 	wire [7:0] switches;
 	
-	always #10 clk <= ~clk;
+	always #62 clk <= ~clk;
 	GBZ80Core core(
 		.clk(clk),
 		.busaddress(addr),