X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/6c46357c6f1bfeefc3a9f85aed03f94e923d09f1..00573fd53c3dc0b2aca146f085d30801a3aed576:/System.v

diff --git a/System.v b/System.v
index 4081771..2bb0613 100644
--- a/System.v
+++ b/System.v
@@ -67,24 +67,24 @@ module CoreTop(
 	output wire [7:0] leds,
 	output serio,
 	output wire [3:0] digits,
-	output wire [7:0] seven);
+	output wire [7:0] seven,
+	output wire hs, vs,
+	output wire [2:0] r, g,
+	output wire [1:0] b);
 	
 	wire clk;	
 	CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
 	
-	wire cclk;
-	IBUFG ibuf (.O(cclk), .I(switches[0]));
-
 	wire [15:0] addr;	
 	wire [7:0] data;
 	wire wr, rd;
 	
-	wire irq, tmrirq;
+	wire irq, tmrirq, lcdcirq, vblankirq;
 	wire [7:0] jaddr;
 	wire [1:0] state;
-
+	
 	GBZ80Core core(
-		.clk(cclk),
+		.clk(clk),
 		.busaddress(addr),
 		.busdata(data),
 		.buswr(wr),
@@ -100,6 +100,20 @@ module CoreTop(
 		.wr(wr),
 		.rd(rd));
 	
+	LCDC lcdc(
+		.addr(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd),
+		.lcdcirq(lcdcirq),
+		.vblankirq(vblankirq),
+		.vgahs(hs),
+		.vgavs(vs),
+		.vgar(r),
+		.vgag(g),
+		.vgab(b));
+	
 	AddrMon amon(
 		.addr(addr), 
 		.clk(clk), 
@@ -107,10 +121,10 @@ module CoreTop(
 		.out(seven),
 		.freeze(buttons[0]),
 		.periods(
-			(state == 2'b00) ? 4'b1000 :
-			(state == 2'b01) ? 4'b0100 :
-			(state == 2'b10) ? 4'b0010 :
-			                   4'b0001) );
+			(state == 2'b00) ? 4'b0010 :
+			(state == 2'b01) ? 4'b0001 :
+			(state == 2'b10) ? 4'b1000 :
+			                   4'b0100) );
 	 
 	Switches sw(
 		.address(addr),
@@ -119,7 +133,7 @@ module CoreTop(
 		.wr(wr),
 		.rd(rd),
 		.ledout(leds),
-		.switches({switches[7:1],1'b0})
+		.switches(switches)
 		);
 
 	UART nouart (	/* no u */
@@ -154,8 +168,8 @@ module CoreTop(
 		.wr(wr),
 		.addr(addr),
 		.data(data),
-		.vblank(0),
-		.lcdc(0),
+		.vblank(vblankirq),
+		.lcdc(lcdcirq),
 		.tovf(tmrirq),
 		.serial(0),
 		.buttons(0),
@@ -175,7 +189,7 @@ module TestBench();
 	wire [7:0] leds;
 	wire [7:0] switches;
 	
-	always #10 clk <= ~clk;
+	always #62 clk <= ~clk;
 	GBZ80Core core(
 		.clk(clk),
 		.busaddress(addr),