X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/6ba4cfea4b24fdd898e90ebd55e95ad43d5d21d4..d1b404569fd0bdc74a3397c4ef0a5c2e5f95c835:/Sound1.v

diff --git a/Sound1.v b/Sound1.v
index 9444dbf..ca97b17 100644
--- a/Sound1.v
+++ b/Sound1.v
@@ -17,24 +17,29 @@ module Sound1(
 	);
 
 	/* can be optimized as register file */
-	reg [7:0] nr10, nr11, nr12, nr13, nr14;
+	reg [7:0] nr10 = 0, nr11 = 0, nr12 = 0, nr13 = 0, nr14 = 0;
 	reg [10:0] counter = 0;
 	reg [4:0] lencnt = 0;
 	reg [3:0] delta = 4'b1111;
-	reg [2:0] dutycnt;
+	reg toggle = 0;
 	reg [3:0] snd_out = 0;
+	
+	reg rdlatch;
+	reg [15:0] addrlatch;
 
 	assign snd_data = en ? snd_out : 0;
 
-	assign data = rd ?
-	                 addr == `ADDR_NR10 ? nr10 :
-	                 addr == `ADDR_NR11 ? nr11 :
-	                 addr == `ADDR_NR12 ? nr12 :
-	                 addr == `ADDR_NR13 ? nr13 :
-	                 addr == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
+	assign data = rdlatch ?
+	                 addrlatch == `ADDR_NR10 ? nr10 :
+	                 addrlatch == `ADDR_NR11 ? nr11 :
+	                 addrlatch == `ADDR_NR12 ? nr12 :
+	                 addrlatch == `ADDR_NR13 ? nr13 :
+	                 addrlatch == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
 	              : 8'bzzzzzzzz;
 
-	always @ (negedge core_clk) begin
+	always @ (posedge core_clk) begin
+		rdlatch <= rd;
+		addrlatch <= addr;
 		if(en && wr) begin
 			case(addr)
 			`ADDR_NR10: nr10 <= data;
@@ -58,15 +63,10 @@ module Sound1(
 			counter <= counter - 1;
 		else begin
 			counter <= ~{nr14[2:0],nr13} + 1;  /* possible A */
-			dutycnt <= dutycnt + 1;
+			toggle <= ~toggle;
 		end
-
-		case (nr11[7:6])
-		2'b00: snd_out <= dutycnt ? 0 : delta;   /* probable A */
-		2'b01: snd_out <= (dutycnt[2:1] == 2'b0) ? delta : 0;
-		2'b10: snd_out <= dutycnt[2] ? delta : 0;
-		2'b11: snd_out <= (dutycnt[2:1] == 2'b0) ? 0 : delta;
-		endcase
+		
+		snd_out <= toggle ? delta : 0;	/* Leave it to Dennis. */
 	end
 
 	always @ (posedge lenclk) begin