X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/6b4e28281b4fa98272bead1eedeea577e8778169..722e486a9ea69af1fdad7d0d31490bb2845881ec:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 0697295..77c3649 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -42,6 +42,8 @@
 `define INSN_JPCC_imm		8'b110xx010
 `define INSN_ALU_A		8'b00xxx111
 `define INSN_JP_HL			8'b11101001
+`define INSN_JR_imm			8'b00011000
+`define INSN_JRCC_imm		8'b001xx000
 
 `define INSN_cc_NZ			2'b00
 `define INSN_cc_Z				2'b01
@@ -485,6 +487,30 @@ module GBZ80Core(
 			`INSN_JP_HL: begin
 				`EXEC_NEWCYCLE;
 			end
+			`INSN_JR_imm,`INSN_JRCC_imm: begin
+				case (cycle)
+				0:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				1: begin
+						`EXEC_INC_PC;
+						if (opcode[5]) begin	// i.e., JP cc,nn
+							/* We need to check the condition code to bail out. */
+							case (opcode[4:3])
+							`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+							endcase
+						end
+					end
+				2:	begin
+						`EXEC_NEWCYCLE;
+					end
+				endcase
+			end
 			default:
 				$stop;
 			endcase
@@ -792,6 +818,15 @@ module GBZ80Core(
 				{registers[`REG_PCH],registers[`REG_PCL]} <=
 					{registers[`REG_H],registers[`REG_L]};
 			end
+			`INSN_JR_imm,`INSN_JRCC_imm: begin
+				case (cycle)
+				0:	begin /* type F */ end
+				1:	tmp <= rdata;
+				2: {registers[`REG_PCH],registers[`REG_PCL]} <=
+						{registers[`REG_PCH],registers[`REG_PCL]} +
+						{tmp[7]?8'hFF:8'h00,tmp};
+				endcase
+			end
 			default:
 				$stop;
 			endcase