X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/6493be2b598bd598f939245dbd8a9ae4b242f407..3785d05a183aa8de851f361432c5da2cc8f11c16:/System.v

diff --git a/System.v b/System.v
index 259656a..8b8d613 100644
--- a/System.v
+++ b/System.v
@@ -21,19 +21,22 @@ module InternalRAM(
 	input clk,
 	input wr, rd);
 	
+	// synthesis attribute ram_style of reg is block
 	reg [7:0] ram [8191:0];
 	
-	wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+	wire decode = address[15:13] == 3'b110;
 	reg [7:0] odata;
 	wire idata = data;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
 	always @(negedge clk)
 	begin
-		if (decode && rd)
+		if (decode)	// This has to go this way. The only way XST knows how to do
+		begin				// block ram is chip select, write enable, and always
+			if (wr)		// reading. "else if rd" does not cut it ...
+				ram[address[12:0]] <= data;
 			odata <= ram[address[12:0]];
-		else if (decode && wr)
-			ram[address[12:0]] <= data;
+		end
 	end
 endmodule
 
@@ -61,14 +64,13 @@ endmodule
 module CoreTop(
 	input xtal,
 	input [7:0] switches,
+	input [3:0] buttons,
 	output wire [7:0] leds,
 	output serio,
 	output wire [3:0] digits,
 	output wire [7:0] seven);
 	
-	wire clk;
-	//IBUFG ibuf (.O(clk), .I(iclk));
-	
+	wire clk;	
 	CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
 
 	wire [15:0] addr;	
@@ -93,7 +95,8 @@ module CoreTop(
     .addr(addr), 
     .clk(clk), 
     .digit(digits), 
-    .out(seven)
+    .out(seven),
+	 .freeze(buttons[0])
     );
 	 
 	Switches sw(
@@ -106,7 +109,7 @@ module CoreTop(
 		.switches(switches)
 		);
 
-	UART nouart (
+	UART nouart (	/* no u */
     .clk(clk), 
     .wr(wr), 
     .rd(rd), 
@@ -114,10 +117,41 @@ module CoreTop(
     .data(data), 
     .serial(serio)
     );
+
+  InternalRAM ram(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd));
+
+	wire irq, tmrirq;
+	wire [7:0] jaddr;
+	Timer tmr(
+		.clk(clk),
+		.wr(wr),
+		.rd(rd),
+		.addr(addr),
+		.data(data),
+		.irq(tmrirq));
+	
+	Interrupt intr(
+		.clk(clk),
+		.rd(rd),
+		.wr(wr),
+		.addr(addr),
+		.data(data),
+		.vblank(0),
+		.lcdc(0),
+		.tovf(tmrirq),
+		.serial(0),
+		.buttons(0),
+		.master(irq),
+		.jaddr(jaddr));
 endmodule
 
 module TestBench();
-	reg clk = 0;
+	reg clk = 1;
 	wire [15:0] addr;
 	wire [7:0] data;
 	wire wr, rd;
@@ -140,12 +174,12 @@ module TestBench();
 		.wr(wr),
 		.rd(rd));
 	
-//	InternalRAM ram(
-//		.address(addr),
-//		.data(data),
-//		.clk(clk),
-//		.wr(wr),
-//		.rd(rd));
+	InternalRAM ram(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd));
 
 	wire serio;
 	UART uart(
@@ -156,6 +190,30 @@ module TestBench();
 		.rd(rd),
 		.serial(serio));
 	
+	wire irq, tmrirq;
+	wire [7:0] jaddr;
+	Timer tmr(
+		.clk(clk),
+		.wr(wr),
+		.rd(rd),
+		.addr(addr),
+		.data(data),
+		.irq(tmrirq));
+	
+	Interrupt intr(
+		.clk(clk),
+		.rd(rd),
+		.wr(wr),
+		.addr(addr),
+		.data(data),
+		.vblank(0),
+		.lcdc(0),
+		.tovf(tmrirq),
+		.serial(0),
+		.buttons(0),
+		.master(irq),
+		.jaddr(jaddr));
+	
 //	Switches sw(
 //		.clk(clk),
 //		.address(addr),