X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/62940da0dd1b60db11e9861d6dd55a43c5756114..9c834ff2149ba2b9b4db71a1bb6b974235c88273:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 095d9e8..ae6ff00 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -46,6 +46,9 @@
 `define INSN_JR_imm			8'b00011000
 `define INSN_JRCC_imm		8'b001xx000
 `define INSN_INCDEC16		8'b00xxx011
+`define INSN_VOP_INTR		8'b11111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
+`define INSN_DI				8'b11110011
+`define INSN_EI				8'b11111011
 
 `define INSN_cc_NZ			2'b00
 `define INSN_cc_Z				2'b01
@@ -89,10 +92,11 @@ module GBZ80Core(
 	input clk,
 	output reg [15:0] busaddress = 0,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] busdata,
-	output reg buswr = 0, output reg busrd = 0);
+	output reg buswr = 0, output reg busrd = 0,
+	input irq, input [7:0] jaddr);
 	
-	reg [1:0] state = 0;					/* State within this bus cycle (see STATE_*). */
-	reg [2:0] cycle = 0;					/* Cycle for instructions. */
+	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
+	reg [2:0] cycle;					/* Cycle for instructions. */
 	
 	reg [7:0] registers[11:0];
 	
@@ -101,14 +105,14 @@ module GBZ80Core(
 	reg [7:0] opcode;				/* Opcode from the current machine cycle. */
 	
 	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
-	reg rd = 1, wr = 0, newcycle = 1;
+	reg rd, wr, newcycle;
 	
 	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
 	
 	reg [7:0] buswdata;
 	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
 	
-	reg ie = 0;
+	reg ie = 0, iedelay = 0;
 	
 	initial begin
 		registers[ 0] <= 0;
@@ -123,12 +127,19 @@ module GBZ80Core(
 		registers[ 9] <= 0;
 		registers[10] <= 0;
 		registers[11] <= 0;
-		ie <= 0;
 		rd <= 1;
 		wr <= 0;
 		newcycle <= 1;
 		state <= 0;
 		cycle <= 0;
+		busrd <= 0;
+		buswr <= 0;
+		busaddress <= 0;
+		ie <= 0;
+		iedelay <= 0;
+		opcode <= 0;
+		state <= `STATE_WRITEBACK;
+		cycle <= 0;
 	end
 
 	always @(posedge clk)
@@ -149,7 +160,10 @@ module GBZ80Core(
 		end
 		`STATE_DECODE: begin
 			if (newcycle) begin
-				opcode <= busdata;
+				if (ie && irq)
+					opcode <= `INSN_VOP_INTR;
+				else
+					opcode <= busdata;
 				rdata <= busdata;
 				newcycle <= 0;
 				cycle <= 0;
@@ -157,6 +171,10 @@ module GBZ80Core(
 				if (rd) rdata <= busdata;
 				cycle <= cycle + 1;
 			end
+			if (iedelay) begin
+				ie <= 1;
+				iedelay <= 0;
+			end
 			buswr <= 0;
 			busrd <= 0;
 			wr <= 0;
@@ -287,7 +305,7 @@ module GBZ80Core(
 					end
 				1:	begin
 						wr <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+						address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
 						case (opcode[5:4])
 						`INSN_stack_AF:	wdata <= registers[`REG_F];
 						`INSN_stack_BC:	wdata <= registers[`REG_C];
@@ -310,7 +328,7 @@ module GBZ80Core(
 					end
 				1:	begin
 						rd <= 1;
-						address <= {registers[`REG_SPH],registers[`REG_SPL]};
+						address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
 					end
 				2:	begin
 						`EXEC_NEWCYCLE;
@@ -552,6 +570,31 @@ module GBZ80Core(
 					end
 				endcase
 			end
+			`INSN_VOP_INTR: begin
+				case (cycle)
+				0:	begin
+						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+						wdata <= registers[`REG_PCH];
+						wr <= 1;
+					end
+				1:	begin
+						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+						wdata <= registers[`REG_PCL];
+						wr <= 1;
+					end
+				2:	begin
+						`EXEC_NEWCYCLE;
+					end
+				endcase
+			end
+			`INSN_DI: begin
+				`EXEC_NEWCYCLE;
+				`EXEC_INC_PC;
+			end
+			`INSN_EI: begin
+				`EXEC_NEWCYCLE;
+				`EXEC_INC_PC;
+			end
 			default:
 				$stop;
 			endcase
@@ -637,18 +680,16 @@ module GBZ80Core(
 			end
 			`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
 				case (cycle)
-				0:	{registers[`REG_SPH],registers[`REG_SPL]} <=
-						{registers[`REG_SPH],registers[`REG_SPL]} - 1;
-				1:	{registers[`REG_SPH],registers[`REG_SPL]} <=
-						{registers[`REG_SPH],registers[`REG_SPL]} - 1;
+				0:	begin /* type F */ end
+				1:	begin /* type F */ end
 				2:	begin /* type F */ end
-				3:	begin /* type F */ end
+				3:	{registers[`REG_SPH],registers[`REG_SPL]} <=
+						{registers[`REG_SPH],registers[`REG_SPL]} - 2;
 				endcase
 			end
 			`INSN_POP_reg: begin	/* POP is 12 cycles! */
 				case (cycle)
-				0:	{registers[`REG_SPH],registers[`REG_SPL]} <=
-						{registers[`REG_SPH],registers[`REG_SPL]} + 1;
+				0:	begin end
 				1:	begin
 						case (opcode[5:4])
 						`INSN_stack_AF:	registers[`REG_F] <= rdata;
@@ -656,8 +697,6 @@ module GBZ80Core(
 						`INSN_stack_DE:	registers[`REG_E] <= rdata;
 						`INSN_stack_HL:	registers[`REG_L] <= rdata;
 						endcase
-						{registers[`REG_SPH],registers[`REG_SPL]} <=
-							{registers[`REG_SPH],registers[`REG_SPL]} + 1;
 					end
 				2:	begin
 						case (opcode[5:4])
@@ -666,6 +705,8 @@ module GBZ80Core(
 						`INSN_stack_DE:	registers[`REG_D] <= rdata;
 						`INSN_stack_HL:	registers[`REG_H] <= rdata;
 						endcase
+						{registers[`REG_SPH],registers[`REG_SPL]} <=
+							{registers[`REG_SPH],registers[`REG_SPL]} + 2;
 					end
 				endcase
 			end
@@ -896,6 +937,21 @@ module GBZ80Core(
 					end
 				endcase
 			end
+			`INSN_VOP_INTR: begin
+				case (cycle)
+				0:	begin end
+				1:	begin end
+				2:	begin
+						ie <= 0;
+						{registers[`REG_PCH],registers[`REG_PCL]} <=
+							{8'b0,jaddr};
+						{registers[`REG_SPH],registers[`REG_SPL]} <=
+							{registers[`REG_SPH],registers[`REG_SPL]} - 2;
+					end
+				endcase
+			end
+			`INSN_DI: ie <= 0;
+			`INSN_EI: iedelay <= 1;
 			default:
 				$stop;
 			endcase