X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/616eebe0bdb3166e9cfda312d6425910b2addf8f..611e4a90d4f4c5b5e2cadde0da57639bfbaca6a8:/System.v

diff --git a/System.v b/System.v
index 996ec10..8bc14e9 100644
--- a/System.v
+++ b/System.v
@@ -31,9 +31,9 @@ module InternalRAM(
 	
 	always @(negedge clk)
 	begin
-		if (decode)
-		begin
-			if (wr)
+		if (decode)	// This has to go this way. The only way XST knows how to do
+		begin				// block ram is chip select, write enable, and always
+			if (wr)		// reading. "else if rd" does not cut it ...
 				ram[address[12:0]] <= data;
 			odata <= ram[address[12:0]];
 		end