X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/5c33c5c001049403ac33d71bfbe0115c318c1b4c..f2b745a710572fd5cb2b1cf97d1d05a9b74d4fe1:/GBZ80Core.v?ds=inline

diff --git a/GBZ80Core.v b/GBZ80Core.v
index f438339..33e7be6 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -52,6 +52,7 @@
 `define INSN_LDH_AC		8'b111x0010	// Either LDH A,(C) or LDH (C),A
 `define INSN_LDx_AHL		8'b001xx010	// LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8		8'b10xxxxxx	// 10 xxx yyy
+`define INSN_ALU8IMM		8'b11xxx110
 `define INSN_NOP		8'b00000000
 `define INSN_RST		8'b11xxx111
 `define INSN_RET		8'b110x1001	// 1 = RETI, 0 = RET
@@ -68,6 +69,8 @@
 `define INSN_VOP_INTR		8'b11111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
 `define INSN_DI			8'b11110011
 `define INSN_EI			8'b11111011
+`define INSN_INCDEC_HL		8'b0011010x
+`define INSN_INCDEC_reg8	8'b00xxx10x
 
 `define INSN_cc_NZ		2'b00
 `define INSN_cc_Z		2'b01
@@ -118,9 +121,10 @@ module GBZ80Core(
 	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] busdata,
 	output reg buswr, output reg busrd,
-	input irq, input [7:0] jaddr);
+	input irq, input [7:0] jaddr,
+	output reg [1:0] state);
 	
-	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
+//	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
 	reg [2:0] cycle;					/* Cycle for instructions. */
 	
 	reg [7:0] registers[11:0];