X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/5509558d05f30339f3393f02f67e8854cbe25a00..6c46357c6f1bfeefc3a9f85aed03f94e923d09f1:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 6039b30..36cd76a 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -107,28 +107,21 @@
 `define INSN_alu_SCF		3'b110
 `define INSN_alu_CCF		3'b111
 
-`define EXEC_INC_PC \
-	`_PC <= `_PC + 1
-`define EXEC_NEXTADDR_PCINC \
-	address <= `_PC + 1
-`define EXEC_NEWCYCLE \
-	begin newcycle <= 1; rd <= 1; wr <= 0; end
-`define EXEC_WRITE(ad, da) \
-	begin address <= (ad); \
-	wdata <= (da); \
-	wr <= 1; end
-`define EXEC_READ(ad) \
-	begin address <= (ad); \
-	rd <= 1; end
+`define EXEC_INC_PC 		`_PC <= `_PC + 1;
+`define EXEC_NEXTADDR_PCINC	address <= `_PC + 1;
+`define EXEC_NEWCYCLE		begin newcycle <= 1; rd <= 1; wr <= 0; end
+`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
+`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end
 
 module GBZ80Core(
 	input clk,
 	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] busdata,
 	output reg buswr, output reg busrd,
-	input irq, input [7:0] jaddr);
+	input irq, input [7:0] jaddr,
+	output reg [1:0] state);
 	
-	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
+//	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
 	reg [2:0] cycle;					/* Cycle for instructions. */
 	
 	reg [7:0] registers[11:0];
@@ -217,19 +210,10 @@ module GBZ80Core(
 			state <= `STATE_EXECUTE;
 		end
 		`STATE_EXECUTE: begin
-
 			casex (opcode)
 			`define EXECUTE
 			`include "allinsns.v"
 			`undef EXECUTE
-			`INSN_DI: begin
-				`EXEC_NEWCYCLE;
-				`EXEC_INC_PC;
-			end
-			`INSN_EI: begin
-				`EXEC_NEWCYCLE;
-				`EXEC_INC_PC;
-			end
 			default:
 				$stop;
 			endcase