X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/5509558d05f30339f3393f02f67e8854cbe25a00..4fd47c85d2419ac8fa788696f7fda03cf3ce8124:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 6039b30..3931bdd 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -52,6 +52,7 @@
 `define INSN_LDH_AC		8'b111x0010	// Either LDH A,(C) or LDH (C),A
 `define INSN_LDx_AHL		8'b001xx010	// LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8		8'b10xxxxxx	// 10 xxx yyy
+`define INSN_ALU8IMM		8'b11xxx110
 `define INSN_NOP		8'b00000000
 `define INSN_RST		8'b11xxx111
 `define INSN_RET		8'b110x1001	// 1 = RETI, 0 = RET
@@ -68,6 +69,11 @@
 `define INSN_VOP_INTR		8'b11111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
 `define INSN_DI			8'b11110011
 `define INSN_EI			8'b11111011
+`define INSN_INCDEC_HL		8'b0011010x
+`define INSN_INCDEC_reg8	8'b00xxx10x
+`define INSN_LD8M_A		8'b111x0000	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+`define INSN_LD16M_A		8'b111x1010	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+`define INSN_LDBCDE_A		8'b000xx010	// 0000 for BC, 0001 for DE, 1010 for A,(x), 0010 for (x),A
 
 `define INSN_cc_NZ		2'b00
 `define INSN_cc_Z		2'b01
@@ -107,28 +113,21 @@
 `define INSN_alu_SCF		3'b110
 `define INSN_alu_CCF		3'b111
 
-`define EXEC_INC_PC \
-	`_PC <= `_PC + 1
-`define EXEC_NEXTADDR_PCINC \
-	address <= `_PC + 1
-`define EXEC_NEWCYCLE \
-	begin newcycle <= 1; rd <= 1; wr <= 0; end
-`define EXEC_WRITE(ad, da) \
-	begin address <= (ad); \
-	wdata <= (da); \
-	wr <= 1; end
-`define EXEC_READ(ad) \
-	begin address <= (ad); \
-	rd <= 1; end
+`define EXEC_INC_PC 		`_PC <= `_PC + 1;
+`define EXEC_NEXTADDR_PCINC	address <= `_PC + 1;
+`define EXEC_NEWCYCLE		begin newcycle <= 1; rd <= 1; wr <= 0; end
+`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
+`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end
 
 module GBZ80Core(
 	input clk,
 	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] busdata,
 	output reg buswr, output reg busrd,
-	input irq, input [7:0] jaddr);
+	input irq, input [7:0] jaddr,
+	output reg [1:0] state);
 	
-	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
+//	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
 	reg [2:0] cycle;					/* Cycle for instructions. */
 	
 	reg [7:0] registers[11:0];
@@ -217,19 +216,10 @@ module GBZ80Core(
 			state <= `STATE_EXECUTE;
 		end
 		`STATE_EXECUTE: begin
-
 			casex (opcode)
 			`define EXECUTE
 			`include "allinsns.v"
 			`undef EXECUTE
-			`INSN_DI: begin
-				`EXEC_NEWCYCLE;
-				`EXEC_INC_PC;
-			end
-			`INSN_EI: begin
-				`EXEC_NEWCYCLE;
-				`EXEC_INC_PC;
-			end
 			default:
 				$stop;
 			endcase