X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/537e1f833b8eba858c06053ea6006ea608b9a5cc..39a68cde9f2a76dabfcc9d7654f212ad1d7b356a:/LCDC.v diff --git a/LCDC.v b/LCDC.v index 41b5500..8f237eb 100644 --- a/LCDC.v +++ b/LCDC.v @@ -16,12 +16,32 @@ module LCDC( inout [7:0] data, input clk, // 8MHz clock input wr, rd, - output reg irq = 0); + output wire lcdcirq, + output wire vblankirq, + output wire lcdclk, lcdvs, lcdhs, + output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb); + + /***** Needed prototypes *****/ + wire [1:0] pixdata; /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/ reg clk4 = 0; always @(posedge clk) clk4 = ~clk4; + assign lcdclk = clk4; + + /***** LCD control registers *****/ + reg [7:0] rLCDC = 8'h91; + reg [7:0] rSTAT = 8'h00; + reg [7:0] rSCY = 8'b00; + reg [7:0] rSCX = 8'b00; + reg [7:0] rLYC = 8'b00; + reg [7:0] rDMA = 8'b00; + reg [7:0] rBGP = 8'b00; + reg [7:0] rOBP0 = 8'b00; + reg [7:0] rOBP1 = 8'b00; + reg [7:0] rWY = 8'b00; + reg [7:0] rWX = 8'b00; /***** Sync generation *****/ @@ -30,45 +50,123 @@ module LCDC( * * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks * 1 -> in vblank and OAM/VRAM available - * 2 -> OAM in use - present 83 clks - * 3 -> OAM/VRAM in use - present 166 clks - * So, X = 0~165 is HActive, - * X = 166-372 is HBlank, - * X = 373-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr. + * 2 -> OAM in use - present 86 clks + * 3 -> OAM/VRAM in use - present 163 clks + * So, X = 0~162 is HActive, + * X = 163-369 is HBlank, + * X = 370-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr. + * [02:15:10] LY is updated near the 0 -> 2 transition + * [02:15:38] it seems to be updated internally first before it is visible in the LY register itself + * [02:15:40] some kind of delay + * [02:16:19] iirc it is updated about 4 cycles prior to mode 2 */ reg [8:0] posx = 9'h000; reg [7:0] posy = 8'h00; + + wire vraminuse = (posx < 163); + wire oaminuse = (posx > 369); + + wire display = (posx > 2) && (posx < 163) && (posy < 144); + wire [1:0] mode = (posy < 144) ? - ((posx < 166) ? 2'b11 : - (posx < 373) ? 2'b00 : - 2'b10) + (vraminuse ? 2'b11 : + oaminuse ? 2'b10 : + 2'b00) : 2'b01; - always @(posedge clk) + assign lcdvs = (posy == 153) && (posx == 455); + assign lcdhs = (posx == 455); + assign lcdr = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000; + assign lcdg = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000; + assign lcdb = display ? {posy < rSCY ? 2'b11 : 2'b00} : 2'b00; + + reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0; + assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq); + assign vblankirq = (posx == 0 && posy == 153); + + always @(posedge clk4) begin if (posx == 455) begin posx <= 0; - if (posy == 153) + if (posy == 153) begin posy <= 0; - else + if (0 == rLYC) + lycirq <= 1; + end else begin posy <= posy + 1; - end else + /* Check for vblank and generate an IRQ if needed. */ + if (posy == 143) begin + mode01irq <= 1; + end + if ((posy + 1) == rLYC) + lycirq <= 1; + + end + end else begin posx <= posx + 1; + if (posx == 165) + mode00irq <= 1; + else if (posx == 373) + mode10irq <= 1; + else begin + mode00irq <= 0; + mode01irq <= 0; + mode10irq <= 0; + end + lycirq <= 0; + end end + + /***** Video RAM *****/ + /* Base is 0x8000 + * + * Tile data from 8000-8FFF or 8800-97FF + * Background tile maps 9800-9BFF or 9C00-9FFF + */ + reg [7:0] tiledata [6143:0]; + reg [7:0] bgmap1 [1023:0]; + reg [7:0] bgmap2 [1023:0]; + + // Upper five bits are Y coord, lower five bits are X coord + wire [7:0] vxpos = rSCX + posx - 3; + wire [7:0] vypos = rSCY + posy; + + // The new tile number is loaded when vxpos[2:0] is 3'b101 + // The new tile data low is loaded when vxpos[2:0] is 3'b110 + // The new tile data high is loaded when vxpos[2:0] is 3'b111 + // The new tile data is latched and ready when vxpos[2:0] is 3'b000! + wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]}; + reg [7:0] tileno; + wire [10:0] tileaddr = {tileno, vypos[2:1]}; + reg [7:0] tilelowtmp, tilehigh, tilelow; + assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]}; + + wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF); + wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF); + + always @(negedge clk) + if (vraminuse) begin + if ((posx == 0) || ((posx > 2) && (vxpos[2:0] == 3'b101))) + tileno <= bgmap1[bgmapaddr]; + else if ((posx == 1) || ((posx > 2) && (vxpos[2:0] == 3'b110))) + tilelowtmp <= tiledata[{tileaddr, 1'b0}]; + else if ((posx == 2) || ((posx > 2) && (vxpos[2:0] == 3'b111))) begin + tilehigh <= tiledata[{tileaddr, 1'b1}]; + tilelow <= tilelowtmp; + end + end else begin + if (decode_tiledata) begin + tilelowtmp <= tiledata[addr[12:0]]; + if (wr) + tiledata[addr[12:0]] <= data; + end else if (decode_bgmap1) begin + tileno <= bgmap1[addr[12:0]]; + if (wr) + bgmap1[addr[12:0]] <= data; + end + end /***** Bus interface *****/ - reg [7:0] rLCDC = 8'h91; - reg [7:0] rSTAT = 8'h00; - reg [7:0] rSCY = 8'b00; - reg [7:0] rSCX = 8'b00; - reg [7:0] rLYC = 8'b00; - reg [7:0] rDMA = 8'b00; - reg [7:0] rBGP = 8'b00; - reg [7:0] rOBP0 = 8'b00; - reg [7:0] rOBP1 = 8'b00; - reg [7:0] rWY = 8'b00; - reg [7:0] rWX = 8'b00; - assign data = rd ? (addr == `ADDR_LCDC) ? rLCDC : (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} : @@ -81,6 +179,8 @@ module LCDC( (addr == `ADDR_OBP1) ? rOBP1 : (addr == `ADDR_WY) ? rWY : (addr == `ADDR_WX) ? rWX : + (decode_tiledata) ? tilelowtmp : + (decode_bgmap1) ? tileno : 8'bzzzzzzzz : 8'bzzzzzzzz;