X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/537e1f833b8eba858c06053ea6006ea608b9a5cc..00573fd53c3dc0b2aca146f085d30801a3aed576:/LCDC.v?ds=sidebyside

diff --git a/LCDC.v b/LCDC.v
index 41b5500..622094a 100644
--- a/LCDC.v
+++ b/LCDC.v
@@ -16,13 +16,29 @@ module LCDC(
 	inout [7:0] data,
 	input clk,	// 8MHz clock
 	input wr, rd,
-	output reg irq = 0);
+	output wire lcdcirq,
+	output wire vblankirq,
+	output wire vgavs, vgahs,
+	output wire [2:0] vgar, vgag, output wire [1:0] vgab);
 	
 	/***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
 	reg clk4 = 0;
 	always @(posedge clk)
 		clk4 = ~clk4;
 	
+	/***** LCD control registers *****/
+	reg [7:0] rLCDC = 8'h91;
+	reg [7:0] rSTAT = 8'h00;
+	reg [7:0] rSCY = 8'b00;
+	reg [7:0] rSCX = 8'b00;
+	reg [7:0] rLYC = 8'b00;
+	reg [7:0] rDMA = 8'b00;
+	reg [7:0] rBGP = 8'b00;
+	reg [7:0] rOBP0 = 8'b00;
+	reg [7:0] rOBP1 = 8'b00;
+	reg [7:0] rWY = 8'b00;
+	reg [7:0] rWX = 8'b00;
+	
 	/***** Sync generation *****/
 	
 	/* A complete cycle takes 456 clocks.
@@ -44,31 +60,51 @@ module LCDC(
 				 2'b10)
 				: 2'b01;
 	
-	always @(posedge clk)
+	assign vgavs = (posy > 147) && (posy < 151);
+	assign vgahs = (posx < 250) && (posx < 350);
+	assign vgar = (posx < 160) && (posy < 144) ? {posy == rLYC ? 3'b111 : 3'b000} : 3'b000;
+	assign vgag = (posx < 160) && (posy < 144) ? {posy < rSCY ? 3'b111 : 3'b000} : 3'b000;
+	assign vgab = (posx < 160) && (posy < 144) ? {2'b11} : 2'b00;
+	
+	reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
+	assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
+	assign vblankirq = (posx == 0 && posy == 153);
+	
+	always @(posedge clk4)
 	begin
 		if (posx == 455) begin
 			posx <= 0;
-			if (posy == 153)
+			if (posy == 153) begin
 				posy <= 0;
-			else
+				if (0 == rLYC)
+					lycirq <= 1;
+			end else begin
 				posy <= posy + 1;
-		end else
+				/* Check for vblank and generate an IRQ if needed. */
+				if (posy == 143) begin 
+					mode01irq <= 1;
+				end
+				if ((posy + 1) == rLYC)
+					lycirq <= 1;
+				
+			end
+		end else begin
 			posx <= posx + 1;
+			if (posx == 165)
+				mode00irq <= 1;
+			else if (posx == 373)
+				mode10irq <= 1;
+			else begin
+				mode00irq <= 0;
+				mode01irq <= 0;
+				mode10irq <= 0;
+			end
+			lycirq <= 0;
+		end
+		
 	end
   
 	/***** Bus interface *****/
-	reg [7:0] rLCDC = 8'h91;
-	reg [7:0] rSTAT = 8'h00;
-	reg [7:0] rSCY = 8'b00;
-	reg [7:0] rSCX = 8'b00;
-	reg [7:0] rLYC = 8'b00;
-	reg [7:0] rDMA = 8'b00;
-	reg [7:0] rBGP = 8'b00;
-	reg [7:0] rOBP0 = 8'b00;
-	reg [7:0] rOBP1 = 8'b00;
-	reg [7:0] rWY = 8'b00;
-	reg [7:0] rWX = 8'b00;
-	
 	assign data = rd ?
 			(addr == `ADDR_LCDC) ? rLCDC :
 			(addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :