X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/4d90f272baf43caf90927ca7e893518d526649e5..7d59dad969a6cd1e42958f4c805d1d373ee04713:/LCDC.v diff --git a/LCDC.v b/LCDC.v index a8bec01..9a111f7 100644 --- a/LCDC.v +++ b/LCDC.v @@ -137,7 +137,7 @@ module LCDC( // The new tile data is latched and ready when vxpos[2:0] is 3'b000! wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]}; reg [7:0] tileno; - wire [10:0] tileaddr = {tileno, vypos[2:1]}; + wire [10:0] tileaddr = {tileno, vypos[2:0]}; reg [7:0] tilehigh, tilelow; assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]}; @@ -166,21 +166,21 @@ module LCDC( /***** Bus interface *****/ assign data = rd ? - (addr == `ADDR_LCDC) ? rLCDC : - (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} : - (addr == `ADDR_SCY) ? rSCY : - (addr == `ADDR_SCX) ? rSCX : - (addr == `ADDR_LY) ? posy : - (addr == `ADDR_LYC) ? rLYC : - (addr == `ADDR_BGP) ? rBGP : - (addr == `ADDR_OBP0) ? rOBP0 : - (addr == `ADDR_OBP1) ? rOBP1 : - (addr == `ADDR_WY) ? rWY : - (addr == `ADDR_WX) ? rWX : - (decode_tiledata && addr[0]) ? tilehigh : - (decode_tiledata && ~addr[0]) ? tilelow : - (decode_bgmap1) ? tileno : - 8'bzzzzzzzz : + ((addr == `ADDR_LCDC) ? rLCDC : + (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} : + (addr == `ADDR_SCY) ? rSCY : + (addr == `ADDR_SCX) ? rSCX : + (addr == `ADDR_LY) ? posy : + (addr == `ADDR_LYC) ? rLYC : + (addr == `ADDR_BGP) ? rBGP : + (addr == `ADDR_OBP0) ? rOBP0 : + (addr == `ADDR_OBP1) ? rOBP1 : + (addr == `ADDR_WY) ? rWY : + (addr == `ADDR_WX) ? rWX : + (decode_tiledata && addr[0]) ? tilehigh : + (decode_tiledata && ~addr[0]) ? tilelow : + (decode_bgmap1) ? tileno : + 8'bzzzzzzzz) : 8'bzzzzzzzz; always @(negedge clk)